ADSP-21477 Datasheet, PDF (24/76 Pages) Analog Devices – SHARC Processor

ADSP-21477/ADSP-21478/ADSP-21479
TIMING SPECIFICATIONS
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times. See
Figure 49 on Page 64 under Test Conditions for voltage refer-
ence levels.
Switching Characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching char-
acteristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
as memory) is satisfied.
Timing Requirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
Core Clock Requirements
The processor’s internal clock (a multiple of CLKIN) provides
the clock signal for timing internal memory, processor core, and
serial ports. During reset, program the ratio between the proces-
sor’s internal clock frequency and external (CLKIN) clock
frequency with the CLK_CFG1–0 pins.
The processor’s internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the processor uses an internal phase-locked loop (PLL,
see Figure 5). This PLL-based clocking minimizes the skew
between the system clock (CLKIN) signal and the processor’s
internal clock.
Voltage Controlled Oscillator (VCO)
In application designs, the PLL multiplier value should be
selected in such a way that the VCO frequency never exceeds
f_VCO specified in Table 20.
• The product of CLKIN and PLLM must never exceed 1/2 of
f_VCO (max) in Table 20 if the input divider is not enabled
(INDIV = 0).
• The product of CLKIN and PLLM must never exceed f_VCO
(max) in Table 20 if the input divider is enabled
(INDIV = 1).
The VCO frequency is calculated as follows:
f_VCO = 2 × PLLM × f_INPUT
f_CCLK = (2 × PLLM × f_INPUT) ÷ PLLD
where:
f_VCO = VCO output
PLLM = Multiplier value programmed in the PMCTL register.
During reset, the PLLM value is derived from the ratio selected
using the CLK_CFG pins in hardware.
PLLD = 2, 4, 8, or 16 based on the divider value programmed on
the PMCTL register. During reset this value is 2.
f_INPUT is the input frequency to the PLL.
f_INPUT = CLKIN when the input divider is disabled, or
CLKIN ÷ 2 when the input divider is enabled.
Note the definitions of the clock periods that are a function of
CLKIN and the appropriate ratio control shown in Table 20. All
of the timing specifications for the peripherals are defined in
relation to t_PCLK. See the peripheral specific section for each
peripheral’s timing information.
Table 18. Clock Periods
Timing
Requirements
t_CK
t_CCLK
t_PCLK
t_SDCLK
Description
CLKIN Clock Period
Processor Core Clock Period
Peripheral Clock Period = 2 × t_CCLK
SDRAM Clock Period = (t_CCLK) × SDCKR
Figure 5 shows core to CLKIN relationships with an external
oscillator or crystal. The shaded divider/multiplier blocks
denote where clock ratios can be set through hardware or soft-
ware using the power management control register (PMCTL).
For more information, see the ADSP-214xx SHARC Processor
Hardware Reference.
Rev. B | Page 24 of 76 | March 2012