ADSP-21477 Datasheet, PDF (28/76 Pages) Analog Devices – SHARC Processor

ADSP-21477/ADSP-21478/ADSP-21479
Clock Signals
The processors can use an external clock or a crystal. See the
CLKIN pin description in Table 11. Programs can configure the
processor to use its internal clock generator by connecting the
necessary components to CLKIN and XTAL. Figure 8 shows the
component connections used for a crystal operating in funda-
mental mode. Note that the clock rate is achieved using a
16.67 MHz crystal and a PLL multiplier ratio 16:1
(CCLK:CLKIN achieves a clock speed of 266 MHz). To achieve
the full core clock rate, programs need to configure the multi-
plier bits in the PMCTL register.
CLKIN
C1
22pF
ADSP-2147x
R1
1MΩ *
Y1
XTAL
R2
47Ω *
C2
22pF
16.67
CHOOSE C1 AND C2 BASED ON THE CRYSTAL Y1.
CHOOSE R2 TO LIMIT CRYSTAL DRIVE POWER.
REFER TO CRYSTAL MANUFACTURER'S SPECIFICATIONS
*TYPICAL VALUES
Reset
Figure 8. 266 MHz Operation (Fundamental Mode Crystal)
Table 21. Reset
Parameter
Min
Max
Unit
Timing Requirements
t_WRST1
RESET Pulse Width Low
4 × t_CK
ns
t_SRST
RESET Setup Before CLKIN Low
8
ns
1 _{Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable}
V_dd and CLKIN (not including start-up time of external clock oscillator).
CLKIN
RESET
t_WRST
Figure 9. Reset
t_SRST
Rev. B | Page 28 of 76 | March 2012