CN-0294 Datasheet, PDF (5/5 Pages) Analog Devices – Increasing the Number of Outputs from a Clock Source Using Low Jitter LVPECL Fanout Buffers

Circuit Note
R&S FSUP 26 Signal Source Analyzer
Settings
Residual Noise [T1 w/o spurs]
Signal Frequency:
999.999516 MHz
Int PHN (1.0 k .. 30.0 M) –56.7 dBc
Signal Level:
–3.86 dBm
Residual PM
0.119 °
Cross Corr Mode
Harmonic 1
Residual FM
4.091 kHz
Internal Ref Tuned
Internal Phase Det
RMS Jitter
0.3304 ps
Phase Noise [dBc/Hz]
RF Atten
5 dB
Top –80 dBc/Hz
Marker 1 [T1]
1 kHz
–101.38 dBc/Hz
Marker 2 [T1]
10 kHz
–104.99 dBc/Hz
LoopBW 300Hz
–90
1
–100
2
1 CLRWR
SMTH 1%
–110
3
2 CLRWR
Phase Detector +20 dB
LOCKED
Marker 3 [T1]
100 kHz
–113.61 dBc/Hz
Marker 4 [T1]
1 MHz
–142.17 dBc/Hz
Spur Power (dBc)
–90
A
–100
–110
–120
–120
–130
–140
–130
4
–140
–150
–160
–150
–160
SPR OFF
TH 0dB
CN-0294
1kHz
10kHz
100kHz
1MHz
10MHz
30MHz
FREQUENCY OFFSET
Figure 7. ADCLK948 Output Phase Noise Measurement Showing 330.4 fs rms Jitter
LEARN MORE
CN0232 Design Support Package:
http://www.analog.com/CN0232-DesignSupport
UG-435 User Guide for the EVAL-ADF4350EB1Z board
UG-068, User Guide for the ADCLK948/PCBZ board
MT-031 Tutorial, Grounding Data Converters and Solving the
Mystery of “AGND” and “DGND”, Analog Devices.
MT-086 Tutorial, Fundamentals of Phase Locked Loops (PLLs),
Analog Devices.
MT-101 Tutorial, Decoupling Techniques, Analog Devices.
ADIsimPLL Design Tool
Data Sheets and Evaluation Boards
ADF4351 Evaluation Board (EVAL-ADF4351EB1Z)
ADCLK948 Evaluation Board (ADCLK948/PCBZ)
ADF4351 Data Sheet
ADCLK948 Data Sheet
REVISION HISTORY
9/12—Revision 0: Initial Version
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CN10989-0-9/12(0)
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