CN-0294 Datasheet, PDF (4/5 Pages) Analog Devices – Increasing the Number of Outputs from a Clock Source Using Low Jitter LVPECL Fanout Buffers

CN-0294
Phase Noise and Jitter Measurement
1. Repeat Step 1 to Step 4 from the Logic Level Measurement
section.
2. Terminate the unused CLK2 output of the
ADCLK948/PCBZ with a 50 Ω load (see Figure 5).
3. Connect the CLK2 output via a SMA cable to the signal
source analyzer (see Figure 5).
4. Measure the jitter performance of the signal.
Figure 6 shows the phase noise at the output of the ADF4351,
and the rms jitter is 325.7 fs. Figure 7 shows the phase noise at
the ADCLK948 output. The rms jitter is 330.4 fs.
The additive jitter of the ADCLK948 can be calculated as
√(330.4² − 325.7²) = 55.5 fs rms. The specified value from
the ADCLK948 data sheet is 75 fs rms.
Circuit Note
ADF4351
EVALUATION BOARD
(EVAL-ADF4351EB1Z)
RFOUTA+
RFOUTA−
POWER
SUPPLY
3.3V
COM
T7
CLK0
CLK0
J4
ADCLK948/PCBZ
EVALUATION BOARD
J2
USB
OUT2
OUT2
50Ω
TERM
PC
SPECTRUM
ANALYZER
(R&S FSUP26)
Figure 5. ADF4351 Phase Noise and Jitter Measurement Setup
R&S FSUP 26 Signal Source Analyzer
Settings
Residual Noise [T1 w/o spurs]
Signal Frequency:
999.999524 MHz
Int PHN (1.0 k .. 30.0 M) –56.8 dBc
Signal Level:
–3.86 dBm
Residual PM
0.117 °
Cross Corr Mode
Harmonic 1
Residual FM
2.939 kHz
Internal Ref Tuned
Internal Phase Det
RMS Jitter
0.3257 ps
Phase Noise [dBc/Hz]
RF Atten
5 dB
Top –70 dBc/Hz
Marker 1 [T1]
1 kHz
–101.53 dBc/Hz
Marker 2 [T1]
10 kHz
–104.91 dBc/Hz
LoopBW 300Hz
–80
–90
1
1 CLRWR
SMTH 1%
–100
2
2 CLRWR
–110
3
Phase Detector +20 dB
LOCKED
Marker 3 [T1]
Marker 4 [T1]
100 kHz
1 MHz
–113.11 dBc/Hz –142.41 dBc/Hz
Spur Power (dBc)
–80
A
–90
–100
–110
–120
–120
–130
–140
–150
–160
–130
4
–140
–150
SPR OFF
TH 0dB
–160
1kHz
10kHz
100kHz
FREQUENCY OFFSET
1MHz
10MHz 30MHz
Figure 6. ADF4351 Output Phase Noise Measurement Showing 325.7 fs rms Jitter
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