CN-0294 Datasheet, PDF(1/5 Page) Analog Devices – Increasing the Number of Outputs from a Clock Source Using Low Jitter LVPECL Fanout Buffers

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CN-0294 Datasheet, PDF (1/5 Pages) Analog Devices – Increasing the Number of Outputs from a Clock Source Using Low Jitter LVPECL Fanout Buffers

Circuit Note

CN-0294

Circuits from the Labâ¢ reference circuits are engineered and

tested for quick and easy system integration to help solve todayâs

analog, mixed-signal, and RF design challenges. For more

information and/or support, visit www.analog.com/CN0294.

Devices Connected/Referenced

ADF4351

Fractional-N PLL Synthesizer with

Integrated VCO

ADCLK948

Clock Fanout Buffer with 8 LVPECL

Outputs

Increasing the Number of Outputs from a Clock Source Using Low Jitter LVPECL

Fanout Buffers

EVALUATION AND DESIGN SUPPORT

Circuit Evaluation Boards

ADF4351 Evaluation Board (EVAL-ADF4351EB1Z)

ADCLK948 Evaluation Board (ADCLK948/PCBZ)

Design and Integration Files

Schematics, Layout Files, Bill of Materials

CIRCUIT FUNCTION AND BENEFITS

Many systems require low jitter multiple system clocks for mixed

signal processing and timing. The circuit shown in Figure 1

interfaces the ADF4351 integrated phase-locked loop (PLL)

and voltage-controlled oscillator (VCO) to the ADCLK948,

which provides up to eight differential, low voltage, positive

emitter coupled logic (LVPECL) outputs from one differential

output of the ADF4351.

3.3V

ADCLK948

VVCO

3.3V

1ÂµF

VDD

FREFIN

16 17 28 10 4 26 6 32

1nF 1nF

VVCO

29 REFIN

51â¦

1 CLK

2 DATA

3 LE

DVDD AVDD CE PDBRF VP SDVDD

RFOUTB+ 14 VVCO

RFOUTBâ 15

ZBIAS

ADF4351

RFOUTA+ 12

4.7kâ¦

22 RSET

RFOUTAâ 13

VTUNE 20

CPOUT 7

SW 5

CPGND SDGND AGND AGNDVCO DGND

31 9 11 18 21 27

22nF

3.3V

VREF0

ZBIAS

1nF

100â¦ 100â¦ VT0

CLK0

100â¦ 100â¦ VT1

180â¦

330nF

82â¦

10nF

CLK1

IN_SEL

VREF1

REFERENCE

LVPECL

Figure 1. ADF4351 PLL Connected to ADCLK948 Fanout Buffer (Simplified Schematic: All Connections and Decoupling Not Shown)

Rev. 0

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