AD9148 Datasheet, PDF (49/73 Pages) Analog Devices – Quad 16-Bit,1 GSPS, TxDAC+ Digital-to-Analog Converter

Preliminary Technical Data
INTERFACE TIMING
The timing diagram for the digital interface port is shown in
Figure 58. The sampling point of the data bus nominally occurs
TBD ps after each edge of the DCI signal and has an uncertainty of
± TBD ps, as illustrated by the sampling interval. The data and
FRAME signals must be valid throughout this sampling interval.
The data and FRAME signals may change at any time between
sampling intervals.
The setup (tS) and hold (tH) times with respect to the edges are
shown in Figure 58. The minimum setup and hold times are
shown in Table 15.
Table 15. Data Port Setup and Hold Times
DCI Delay
Minimum Setup
(Register 0x72[1:0]) Time, tS (ns)
Minimum Hold
Time, tH (ns)
00
TBD
TBD
01
TBD
TBD
10
TBD
TBD
11
TBD
TBD
The data interface timing can be verified by using the SED
circuitry. See the Interface Timing Validation section for details.
In data rate mode with synchronization enabled, a second timing
constraint between DCI and DACCLK must be met in addition
to the DCI-to-data timing shown in Table 16. In data rate mode,
only one FIFO slot is being used. The DCI to DACCLK timing
restriction is required to prevent data being written to and read
from the FIFO slot at the same time. The required timing
between DCI and DACCLK is shown in Figure 57.
t_DATA
SAMPLING
INTERVAL
AD9148
DACCLK/
REFCLK
t_DATA
SAMPLING
INTERVAL
DCI
t_SDCI
t_HDCI
Figure 57. Timing Diagram for Input Data Port (Data Rate Mode with Sync On)
Table 16. DCI to DACCLK Setup and Hold Times vs. DCI
Delay Value
DCI Delay
(Register 0x72[1:0])
Minimum Setup
Time, tSDCI (ns)
Minimum Hold
Time, tHDCI (ns)
00
TBD
TBD
01
TBD
TBD
10
TBD
TBD
11
TBD
TBD
SAMPLING
INTERVAL
t_S
t_H
Figure 58. Timing Diagram for Input Data Ports
Rev. PrA | Page 49 of 73