AD9148 Datasheet, PDF (26/73 Pages) Analog Devices – Quad 16-Bit,1 GSPS, TxDAC+ Digital-to-Analog Converter

AD9148
Preliminary Technical Data
Register Name
Data Format
Interrupt Enable 0
Interrupt Enable 1
Addr
(Hex) Bit
03 7
6
5
4
3
2
04 7
6
5
4
2
1
0
05 4
3
2
Name
Function
Binary format
Input data is in twos complement format (0) or unsigned
binary format (1).
Q first enable
Indicates I/Q data pairing on data input; I first (0), Q first (1).
Dual port mode
Number of input data ports used.
Single port (0), dual port (1).
Bus swap
0 = normal data input bus pin out (MSB to LSB).
1 = inverted data input bus pin out (LSB to MSB).
Byte mode
0 = data input bus is 16-bit wide on each port.
1 = data input bus is two 8-bit wide buses on Port A.
Byte swap
0 = normal data input bus pin out (MSB to LSB).
1 = inverted data input bus pin out (LSB to MSB).
Enable PLL lock lost Enables interrupt for PLL lock lost.
Enable PLL lock
Enables interrupt for PLL lock.
Enable sync
lock lost
Enables interrupt for sync lock lost.
Enable sync lock Enables interrupt for sync lock.
Enable FIFO
SPI aligned
Enables interrupt for FIFO SPI aligned.
Enable FIFO
Warning 1
Enables interrupt for FIFO Warning 1.
Enable FIFO
Warning 2
Enables interrupt for FIFO Warning 2.
Enable AED
compare pass
Enable interrupt for AED compare pass.
Enable AED
compare fail
Enables interrupt for AED compare fail.
Enable SED
compare fail
Enables interrupt for SED compare fail.
Default
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Rev. PrA | Page 26 of 73