AD9148 Datasheet, PDF (42/73 Pages) Analog Devices – Quad 16-Bit,1 GSPS, TxDAC+ Digital-to-Analog Converter

AD9148
Preliminary Technical Data
Nominally, data is written to the FIFO at the same rate as data is
read from the FIFO. This keeps the data level in the FIFO constant.
If data is written to the FIFO faster than data is read, the data
level in the FIFO increases. If the data is written to the device
slower than data is read, the data level in the FIFO decreases. For
maximum timing margin, the FIFO level should be maintained
near half full, which is the same as maintaining a difference of
four between the write pointer and read pointer values.
SYNCHRONIZING AND RESETTING THE FIFO
To avoid any concurrent read and write to the same FIFO address
and assure a fixed pipeline delay, it is important to reset the
state of the FIFOs pointers to known states. The pipeline delay
in the AD9148 comes from two sources, FIFO delay and the
delay though the signal processing in the DAC.
To assure a fixed and predictable pipeline delay in the signal
processing, the FIFO read operation is synchronized with the
DACCLK and, more importantly, in case of interpolation, its
divided down version so that the same edge of the slowest clock
in the signal processing reads the same data in the FIFO. The
synchronization is performed by resetting the FIFO read
pointer to a known state relative to the slowest clock used in the
signal processing. This synchronization is enabled by setting
Bit 7 in Register 0x10 to 1, and it uses the REFCLK/SYNC
signal for its reference.
To manage the FIFO pipeline delay, the FIFO write pointer needs
to be synchronized with the read pointer to avoid concurrent
access to the FIFO and to potentially compensate for any data
input phase mismatch. This synchronization can be performed
either at the data rate (see the Data Rate Synchronization section)
or at the FIFO rate (see the FIFO Rate Synchronization section).
Data Rate Synchronization
In this mode, the REFCLK/SYNC signal is used to reset the
FIFO read pointer to 0. The edge of the CLK used to sample the
SYNC signal is selected by Bit 3 of Register 0x10. If the PLL is
used, REFCLK is used as a SYNC signal and the FIFO read
pointer is reset at the REFCLK rate divided by 64. The data rate
synchronization is selected by setting Bit 6 of Register 0x10 to 0.
As previously mentioned, the FRAME signal is used to reset the
FIFO write pointer. When the FRAME is asserted, the FIFO
write pointer is reset to the address defined in Bits[2:0] of the
corresponding FIFO Status/Control Port x register (Register 0x17
or Register 0x19) the next time the read pointer becomes 0, see
Figure 50.
The data rate synchronization, the write pointer of the FIFO,
and the read pointer of the FIFO are synchronized at the SYNC
rate and have a fixed phase offset.
SYNC
RDPTRA 3
4
5
6
7
0
1
2
3
4
5
6
RDPTRB 3
4
5
6
7
0
1
2
3
4
5
6
FRAMEA
FIFO_A WRITE
RESET
RESET VALUE FOR
REGISTER 0x17[2:0] = 0b100
WRPTRA 7
0
1
2
3
4
5
6
7
0
1
2
FRAMEB
FIFO_B WRITE
RESET
RESET VALUE FOR
REGISTER 0x19[2:0] = 0b100
WRPTRB
0
1
2
3
4
4
5
6
7
0
1
2
Figure 50. Timing of the FRAME Input vs. Write Pointer Value in Data Rate
Synchronization
FIFO Rate Synchronization
FIFO Synchronization Modes
To benefit from the advantages of the FIFO functionality in the
different modes of operations, PLL on/off, standalone, or multi-
chip synchronization, the FIFO can operate in the following
ways:
• Synchronization at the data rate
• Synchronization at the FIFO rate (data rate/FIFO depth)
• No synchronization
As discussed in the Input Data Ports section, in single-port
mode and byte mode, the FRAME input is used as a data select
signal that indicates to which DAC the input data is intended to
be written. When synchronization is needed, the FRAME signal
is given another function, initializing the FIFO write pointer
address. When the FRAME signal is asserted high for at least the
time interval needed to load complete data to the four DACs
(which correspond to one DCI period in dual-port mode and
two DCI periods in single-port mode or byte mode) the FIFO
write pointer is reset to a value dependent on the synchronization
mode selected and the FIFO phase offset bits of the corresponding
FIFO Status/Control Port x register, Register 0x17 or Register 0x19.
In this mode, the REFCLK/SYNC signal is used to reset the FIFO
read pointer to 0. The edge of the CLK used to sample the SYNC
signal is selected by Bit 3 of Register 0x10. As previously
mentioned, the FRAME signal is used to reset the FIFO write
pointer. In the FIFO rate synchronization mode, the FIFO write
pointer is reset immediately after the FRAME signal is asserted
high for at least the time interval needed to load complete data to
the four DACs, and the FIFO write pointer is reset to the address
defined in Bits[2:0] of the corresponding FIFO Status/Control
Port x register, Address 0x17 or Address 0x19, see Figure 51.
SYNC
FIFO_A AND FIFO_B
READ RESET
RDPTRA 0
1
2
3
4
5
6
7
0
1
2
3
RDPTRB 0
1
2
3
4
5
6
7
0
1
2
3
FRAMEA
FIFO_A WRITE
RESET
RESET VALUE FOR
REGISTER 0x17[2:0] = 0b100
WRPTRA 4
4
5
6
7
0
1
2
3
4
5
6
FRAMEB
FIFO_B WRITE
RESET
RESET VALUE FOR
REGISTER 0x19[2:0] = 0b110
WRPTRB
2
3
4
6
70
1
2
3
4
56
Figure 51. Timing of the FRAME Input vs. Write Pointer Value in
FIFO Rate Synchronization
Rev. PrA | Page 42 of 73