AD9148 Datasheet, PDF (33/73 Pages) Analog Devices – Quad 16-Bit,1 GSPS, TxDAC+ Digital-to-Analog Converter

Preliminary Technical Data
AD9148
Register Name
Coeff Q Byte 2
Coeff Q Byte 3
I Phase Adj LSB
I Phase Adj MSB
Q Phase Adj LSB
Q Phase Adj MSB
I DC Offset LSB
I DC Offset MSB
Q DC Offset LSB
Q DC Offset MSB
Addr
(Hex) Bit
26 7:5
4
3:0
27 7
6:0
28 7:0
29 1:0
2A 7:0
2B 1:0
2C 7:0
2D 7:0
2E 7:0
2F 7:0
Name
Coeff_4q[2:0]
0
Coeff_3q[6:3]
0
Coeff_4q[9:3]
Phase Word I[7:0]
Phase Word I[9:8]
Phase Word Q[7:0]
Phase Word Q[9:8]
DC Offset I[7:0]
DC Offset I[15:8]
DC Offset Q[7:0]
DC Offset Q[15:8]
Function
Default
Q-Path DAC Sinc^-1 Filter Coefficient 5 (LSB) in twos
0
complement format.
Set this bit to 0.
0
Q-Path DAC Sinc^-1 Filter Coefficient 4 (MSB) in twos
D
complement format.
Set DAC SPI select = 0 to configure DAC 2 path.
Set DAC SPI select = 1 to configure DAC 4 path.
Set this bit to 0.
0
Q-Path DAC Sinc^-1 Filter Coefficient 5 (MSB) in twos
0
complement format.
Set DAC SPI select = 0 to configure DAC 2 path.
Set DAC SPI select = 1 to configure DAC 4 path.
See Register 0x29.
0
Phase Word I[9:0] is used to insert a phase offset between the 0
I and Q data paths.
Set DAC SPI select = 0 to configure DAC 1 path.
Set DAC SPI select = 1 to configure DAC 3 path.
See Register 0x2B.
0
Phase Word Q[9:0] is used to insert a phase offset between 0
the I and Q data paths.
Set DAC SPI select = 0 to configure DAC 2 path.
Set DAC SPI select = 1 to configure DAC 4 path.
See Register 0x2D.
0
DC Offset I[15:0] is a value added directly to the samples
written to the IDAC. The LSB bit weight is 2⁰.
Set DAC SPI select = 0 to configure DAC 1 path.
0
Set DAC SPI select = 1 to configure DAC 3 path.
See Register 0x2F.
0
DC Offset Q[15:0] is a value added directly to the samples
written to the QDAC. The LSB bit weight is 2⁰.
Set DAC SPI select = 0 to configure DAC 2 path.
0
Set DAC SPI select = 1 to configure DAC 4 path.
0
Rev. PrA | Page 33 of 73