AD9164 Datasheet, PDF (46/137 Pages) Analog Devices – DAC update rate up to 12 GSPS

Data Sheet
AD9164
Link Delay Setup Example, Without Known Delay
If the system delays are not known, the AD9164 can read back
the link latency between LMFCRX for each link and the SYSREF±
aligned LMFC. This information is then used to calculate
LMFCVar and LMFCDel.
Figure 107 shows how DYN_LINK_LATENCY_0 (Register 0x302)
provides a readback showing the delay (in PCLK cycles)
between LMFCRX and the transition from ILAS to the first data
sample. By repeatedly power cycling and taking this measurement,
the minimum and maximum delays across power cycles can be
determined and used to calculate LMFCVar and LMFCDel.
In Figure 107, for Link A, Link B, and Link C, the system
containing the AD9164 (including the transmitter) is power
cycled and configured 20 times. The AD9164 is configured as
described in the Sync Procedure section. Because the purpose
of this exercise is to determine LMFCDel and LMFCVar, the
LMFCDel value is programmed to 0 and the DYN_LINK_
LATENCY_0 value is read from Register 0x302. The variation
in the link latency over the 20 runs is shown in Figure 107,
described as follows:
• Link A gives readbacks of 6, 7, 0, and 1. Note that the set of
recorded delay values rolls over the edge of a multiframe at
the boundary of K/ PCLK Factor = 8. Add the number of
PCLK cycles per multiframe = 8 to the readback values of 0
and 1 because they rolled over the edge of the multiframe.
Delay values range from 6 to 9.
• Link B gives delay values from 5 to 7.
• Link C gives delay values from 4 to 7.
The example shown in Figure 107 is demonstrated in the
following steps. Note that this example is in Subclass 1 to
achieve deterministic latency, which has a PCLK Factor
(FrameRate ÷ PCLK Rate) of 4 and uses K = 32; therefore PCLK
cycles per multiframe = 8.
1. Calculate the minimum of all delay measurements across
all power cycles, links, and devices as follows:
MinDelay = min(all Delay values) = 4
2. Calculate the maximum of all delay measurements across
all power cycles, links, and devices as follows:
MaxDelay = max(all Delay values) = 9
3. Calculate the total delay variation (with guard band) across
all power cycles, links, and devices as follows:
LMFCVar = (MaxDelay + 1) − (MinDelay − 1)
= (9 + 1) − (4 − 1) = 10 − 3 = 7 PCLK cycles
4. Calculate the minimum delay in PCLK cycles (with guard
band) across all power cycles, links, and devices as follows:
LMFCDel = (MinDelay − 1) % (K/PCLK Factor)
= (4 − 1) % 32/4
= 3 % 8 = 3 PCLK cycles
5. Write LMFCDel to Register 0x304 for all devices in the system.
Write LMFCVar to Register 0x306 for all devices in the system.
SYSREF±
LMFC_RX
ALIGNED DATA
ILAS
DATA
DYN_LINK_LATENCY
Figure 106. DYN_LINK_LATENCY_x Illustration
LMFC
PCLK
FRAME CLOCK
DYN_LINK_LATENCY_CNT 0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
ALIGNED DATA (LINK A)
ILAS
DATA
ALIGNED DATA (LINK B)
ILAS
DATA
ALIGNED DATA (LINK C)
ILAS
DATA
LMFC_RX
DETERMINISTICALLY
DELAYED DATA
ILAS
LMFC_DELAY = 6
(FRAME CLOCK CYCLES)
LMFC_VAR = 7
(P_CLK CYCLES)
Figure 107. Multilink Synchronization Settings, Derived Method Example
DATA
Rev. A | Page 45 of 136