AD9164 Datasheet, PDF (1/137 Pages) Analog Devices – DAC update rate up to 12 GSPS

Data Sheet
16-Bit, 12 GSPS,
RF DAC and Direct Digital Synthesizer
AD9164
FEATURES
DAC update rate up to 12 GSPS (minimum)
Direct RF synthesis at 6 GSPS (minimum)
DC to 2.5 GHz in baseband mode
DC to 6 GHz in 2× nonreturn-to-zero (NRZ) mode
1.5 GHz to 7.5 GHz in Mix-Mode
Bypassable interpolation
2×, 3×, 4×, 6×, 8×, 12×, 16×, 24×
Excellent dynamic performance
APPLICATIONS
Broadband communications systems
DOCSIS 3.1 cable modem termination system (CMTS)/
video on demand (VOD)/edge quadrature amplitude
modulation (EQAM)
Wireless communications infrastructure
W-CDMA, LTE, LTE-A, point to point
GENERAL DESCRIPTION
The AD9164¹ is a high performance, 16-bit digital-to-analog
converter (DAC) and direct digital synthesizer (DDS) that
supports update rates to 6 GSPS. The DAC core is based on a
quad-switch architecture coupled with a 2× interpolator filter
that enables an effective DAC update rate of up to 12 GSPS in
some modes. The high dynamic range and bandwidth makes
these DACs ideally suited for the most demanding high speed
radio frequency (RF) DAC applications.
The DDS consists of a bank of 32, 32-bit numerically controlled
oscillators (NCOs), each with its own phase accumulator.
When combined with a 100 MHz serial peripheral interface (SPI)
and fast hop modes, phase coherent fast frequency hopping (FFH)
is enabled, with several modes to support multiple applications.
In baseband mode, wide analog bandwidth capability combines
with high dynamic range to support DOCSIS 3.1 cable infrastruc-
ture compliance from the minimum of one carrier up to the full
maximum spectrum of 1.791 GHz of signal bandwidth. A 2×
interpolator filter (FIR85) enables the AD9164 to be configured
for lower data rates and converter clocking to reduce the overall
system power and ease the filtering requirements. In Mix-Mode™
operation, the AD9164 can reconstruct RF carriers in the second
and third Nyquist zones up to 7.5 GHz while still maintaining
exceptional dynamic range. The output current can be programmed
from 8 mA to 38.76 mA. The AD9164 data interface consists of
up to eight JESD204B serializer/deserializer (SERDES) lanes
that are programmable in terms of lane speed and number of
lanes to enable application flexibility.
An SPI interface configures the AD9164 and monitors the status of
all registers. The AD9164 is offered in an 165-ball, 8 mm × 8 mm,
0.5 mm pitch CSP_BGA package, and an 169-ball, 11 mm × 11 mm,
0.8 mm pitch, CSP_BGA package, including a leaded ball option.
PRODUCT HIGHLIGHTS
1. High dynamic range and signal reconstruction bandwidth
supports RF signal synthesis of up to 7.5 GHz.
2. Up to eight lanes JESD204B SERDES interface flexible in
terms of number of lanes and lane speed.
3. Bandwidth and dynamic range to meet DOCSIS 3.1
compliance and multiband wireless communications
standards with margin.
FUNCTIONAL BLOCK DIAGRAM
RESET IRQ
ISET VREF
SDIO
SDO
CS
SCLK
SERDIN0±
SERDIN7±
SYNCOUT±
SYSREF±
SPI
JESD
HB
2×
HB
3×
AD9164
HB
2×
NCO
VREF
NRZ RZ MIX
INV
SINC
DAC
CORE
OUTPUT±
HB
TO JESD
CLOCK
2×,
TO DATAPATH
DISTRIBUTION
4×,
8×
TX_ENABLE
Figure 1.
CLK±
1 _{Protected by U.S. Patents 6,842,132 and 7,796,971.}
Rev. A
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