AD9164 Datasheet, PDF (42/137 Pages) Analog Devices – DAC update rate up to 12 GSPS

Data Sheet
Syncing LMFC Signals
The first step in guaranteeing synchronization across links and
devices begins with syncing the LMFC signals. In Subclass 0,
the LMFC signal is synchronized to an internal processing
clock. In Subclass 1, LMFC signals are synchronized to an
external SYSREF± signal.
SYSREF± Signal
The SYSREF± signal is a differential source synchronous input that
synchronizes the LMFC signals in both the transmitter and receiver
in a JESD204B Subclass 1 system to achieve deterministic latency.
The SYSREF± signal is a rising edge sensitive signal that is
sampled by the device clock rising edge. It is best practice that the
device clock and SYSREF± signals be generated by the same
source, such as the HMC7044 clock generator, so that the phase
alignment between the signals is fixed. When designing for
optimum deterministic latency operation, consider the timing
distribution skew of the SYSREF± signal in a multipoint link
system (multichip).
The AD9164 supports a periodic SYSREF± signal. The periodicity
can be continuous, strobed, or gapped periodic. The SYSREF±
signal can always be dc-coupled (with a common-mode voltage
of 0 V to 1.25 V). When dc-coupled, a small amount of common-
mode current (<500 µA) is drawn from the SYSREF± pins. See
Figure 100 and Figure 101 for the SYSREF± internal circuit.
To avoid this common-mode current draw, use a 50% duty cycle
periodic SYSREF± signal with ac coupling capacitors. If ac-coupled,
the ac coupling capacitors combine with the resistors shown in
Figure 100 or Figure 101 to make a high-pass filter with an RC
time constant of τ = RC. Select C such that τ > 4/SYSREF±
frequency. In addition, the edge rate must be sufficiently fast to
meet the SYSREF± vs. DAC clock keep out window (KOW)
requirements.
It is possible to use ac-coupled mode without meeting the
frequency to time constant constraints (τ = RC and τ > 4/SYSREF±
frequency) by using SYSREF± hysteresis (Register 0x088 and
Register 0x089). However, using hystereis increases the DAC
clock KOW (Table 6 does not apply) by an amount depending
on the SYSREF± frequency, level of hysteresis, capacitor choice,
and edge rate.
SYSREF+
200Ω
100Ω
SYSREF–
200Ω
Figure 100. SYSREF± Input Circuit for the 8 mm × 8 mm 165-Ball BGA
AD9164
SYSREF+
50Ω
3kΩ
19kΩ
50Ω
19kΩ
3kΩ
SYSREF–
Figure 101. SYSREF± Input Circuit for the 11 mm × 11 mm 169-Ball BGA
Sync Processing Modes Overview
The AD9164 supports several LMFC sync processing modes.
These modes are one shot, continuous, and monitor modes. All
sync processing modes perform a phase check to confirm that the
LMFC is phase aligned to an alignment edge. In Subclass 1, the
SYSREF± rising edge acts as the alignment edge; in Subclass 0, an
internal processing clock acts as the alignment edge.
The SYSREF± signal is sampled by a divide by 4 version of the
DAC clock. After SYSREF± is sampled, the phase of the (DAC
clock) ÷4 used to sample SYSREF± is stored in Register 0x037,
Bits[7:0] and Register 0x038, Bits[3:0] as a thermometer code. This
offset can be used by the SERDES data transmitter (for example,
FPGA) to align multiple DACs by accounting for this clock offset
when transmitting data. The sync modes are described below. See
the Sync Procedure section for details on the procedure for
syncing the LMFC signals.
One Shot Sync Mode (SYNCMODE = Register 0x03A,
Bits[1:0] = 0b10)
In one shot sync mode, a phase check occurs on only the first
alignment edge that is received after the sync machine is armed.
After the phase is aligned on the first edge, the AD9164 transitions
to monitor mode. Though an LMFC synchronization occurs only
once, the SYSREF± signal can still be continuous. In this case,
the phase is monitored and reported, but no clock phase
adjustment occurs.
Continuous Sync Mode (SYNCMODE = Register 0x03A,
Bits[1:0] = 0b01)
Continuous mode must be used in Subclass 1 only with a periodic
SYSREF± signal. In continuous mode, a phase check/alignment
occurs on every alignment edge.
Continuous mode differs from one shot mode in two ways.
First, no SPI cycle is required to arm the device; the alignment
edge seen after continuous mode is enabled results in a phase
check. Second, a phase check occurs on every alignment edge in
continuous mode.
Monitor Sync Mode (SYNCMODE = Register 0x03A,
Bits[1:0]) = 0b00)
In monitor mode, the user can monitor the phase error in real time.
Use this sync mode with a periodic SYSREF± signal. The phase is
monitored and reported, but no clock phase adjustment occurs.
Rev. A | Page 41 of 136