ADSP-2191M_15 Datasheet, PDF (41/48 Pages) Analog Devices – DSP Microcomputer

t_DECAY
=
C_-----L---∆_----V_---
I_L
The output disable time t_DIS is the difference between t_MEASURED
and t_DECAY as shown in Figure 26. The time t_MEASURED is the
interval from when the reference signal switches to when the
output voltage decays –V from the measured output high or
output low voltage. The t_DECAY is calculated with test loads C_L
and I_L, and with –V equal to 0.5 V.
REFERENCE
SIGNAL
t_DIS
V_{OH (MEASURED)}
V_{OL (MEASURED)}
t_MEASURED
t_ENA
V_{OH (MEASURED)} – ⌬V 2.0V
V_{OL (MEASURED)} + ⌬V 1.0V
t_DECAY
OUTPUT STOPS
DRIVING
OUTPUT STARTS
DRIVING
HIGH IMPEDANCE STATE.
TEST CONDITIONS CAUSE THIS VOLTAGE
TO BE APPROXIMATELY 1.5V
Figure 26. Output Enable/Disable
I_OL
TO
OUTPUT
PIN
50pF
1.5V
I_OH
Figure 27. Equivalent Device Loading for AC
Measurements (Includes All Fixtures)
INPUT
OR
OUTPUT
1.5V
1.5V
Figure 28. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start
driving. The output enable time t_ENA is the interval from when a
reference signal reaches a high or low voltage level to when the
ADSP-2191M
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram (Figure 26). If multiple
pins (such as the data bus) are enabled, the measurement value
is that of the first pin to start driving.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t_DECAY using the equation at Output Disable Time
on Page 40. Choose –V to be the difference between the
ADSP-2191M’s output voltage and the input threshold for the
device requiring the hold time. A typical –V will be 0.4 V. C_L is
the total bus capacitance (per data line), and I_L is the total leakage
or three-state current (per data line). The hold time will be t_DECAY
plus the minimum disable time (i.e., t_DATRWH for the
write cycle).
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
50 pF on all pins (see Figure 30). The delay and hold specifica-
tions given should be derated by a factor of 1.5 ns/50 pF for loads
other than the nominal value of 50 pF. Figure 28 and Figure 29
show how output rise time varies with capacitance. These figures
also show graphically how output delays and holds vary with load
capacitance. (Note that this graph or derating does not apply to
output disable delays; see Output Disable Time on Page 40.) The
graphs in these figures may not be linear outside the ranges
shown.
40
30
RISE TIME
20
FALL TIME
10
0
0
50
100
150
200
250
LOAD CAPACITANCE – pF
Figure 29. Typical Output Rise Time (10%-90%,
V_DDEXT = Minimum at Maximum Ambient Operating
Temperature) vs. Load Capacitance
Environmental Conditions
The thermal characteristics in which the DSP is operating
influence performance.
Thermal Characteristics
The ADSP-2191M comes in a 144-lead LQFP or 144-lead Ball
Grid Array (mini-BGA) package. The ADSP-2191M is specified
for an ambient temperature (T_AMB) as calculated using the
formula below.
REV. A
–41–