ADSP-2191M_15 Datasheet, PDF (29/48 Pages) Analog Devices – DSP Microcomputer

ADSP-2191M
Host Port ALE Mode Read Cycle Timing
Table 17 and Figure 16 describe Host port read operations in
Address Latch Enable (ALE) mode. For more information on
ACK, Ready, ALE, and ACC mode selection, see the Host port
modes description on Page 8.
Table 17. Host Port ALE Mode Read Cycle Timing
Parameter
Switching Characteristics
t_RHKS1
t_RHKS2
t_RHKH
t_RHS
t_RHH
HRD Asserted to HACK Asserted (ACK Mode) First Byte
HRD Asserted to HACK Asserted (Setup, ACK Mode)²
HRD Deasserted to HACK Deasserted (Hold, ACK Mode)
HRD Asserted to HACK Asserted (Setup, Ready Mode)
HRD Asserted to HACK Deasserted (Hold, Ready Mode)
First Byte
t_RDH
HRD Deasserted to Data Invalid (Hold)
t_RDD
HRD Deasserted to Data Disable
Min
12t_HCLK
12t_HCLK
1
Max
15t_HCLK +t_NH¹
12
10
10
15t_HCLK +t_NH¹
10
Unit
ns
ns
ns
ns
ns
ns
ns
Timing Requirements
t_CSAL
HCMS or HCIOMS Asserted to HALE Asserted (Delay)
0
ns
t_ALCS
HALE Deasserted to Optional HCMS or HCIOMS
1
ns
Deasserted
t_RCSW
HRD Deasserted to HCMS or HCIOMS Deasserted
0
ns
t_ALR
HALE Deasserted to HRD Asserted
5
ns
t_RCS
HRD Deasserted (After Last Byte) to HCMS or
0
ns
HCIOMS Deasserted (Ready for Next Read)
t_ALPW
HALE Asserted Pulsewidth
4
ns
t_HKRD
HACK Asserted to HRD Deasserted (Hold, ACK Mode)
1.5
ns
t_AALS
Address Valid to HALE Deasserted (Setup)
2
ns
t_ALAH
HALE Deasserted to Address Invalid (Hold)
4
ns
1_{tNH are peripheral bus latencies (n ؋tHCLK); these are internal DSP latencies related to the number of peripherals attempting to access DSP memory at}
the same time.
2_{Measurement is for the second, third, or fourth byte of a host read transaction. The quantity of bytes to complete a host read transaction is dependent on}
the data bus size (8 or 16 bits) and the data type (16 or 24 bits).
REV. A
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