ADSP-2191M_15 Datasheet, PDF (37/48 Pages) Analog Devices – DSP Microcomputer

Serial Peripheral Interface (SPI) Port—Slave Timing
Table 21 and Figure 22 describe SPI port slave operations.
Table 21. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter
Switching Characteristics
t_DSOE
t_DSDHI
SPISS Assertion to Data Out Active
SPISS Deassertion to Data High Impedance
t_DDSPID
SCLK Edge to Data Out Valid (Data Out Delay)
t_HDSPID
SCLK Edge to Data Out Invalid (Data Out Hold)
Timing Requirements
t_SPICHS
t_SPICLS
t_SPICLK
t_HDS
t_SPITDS
t_SDSCI
t_SSPID
t_HSPID
Serial Clock High Period
Serial Clock Low Period
Serial Clock Period
Last SPICLK Edge to SPISS Not Asserted
Sequential Transfer Delay
SPISS Assertion to First SPICLK Edge
Data Input Valid to SCLK Edge (Data Input Setup)
SCLK Sampling Edge to Data Input Invalid (Data In Hold)
Min
0
0
0
0
2t_HCLK
2t_HCLK
4t_HCLK
2t_HCLK
2t_HCLK + 4
2t_HCLK
1.6
2.4
ADSP-2191M
Max
8
10
10
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SPISS
(INPUT)
SCLK
(CPOL = 0)
(INPUT)
SCLK
(CPOL = 1)
(INPUT)
t_DSOE
MISO
(OUTPUT)
CPHA = 1
MOSI
(INPUT)
t_DSOE
MISO
(OUTPUT)
CPHA = 0
MOSI
(INPUT)
t_SPICHS
t_SPICLS
t_SPICLK
t_HDS
t_SPITDS
t_SPICLS
t_SDSCI
t_{S PIC HS}
t_DDSPID t_HDSPID
MSB
t_SSPID
MSB
VALID
t_DDSPID
t_HSPID
MSB
MSB
VALID
t_DDSPID
t_DSDHI
LSB
t_SSPID
LSB
VALID
t_HSPID
t_DSDHI
LSB
t_SSPID
LSB
VALID
t_HSPID
Figure 22. Serial Peripheral Interface (SPI) Port—Slave Timing
REV. A
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