ADSP-2191M_15 Datasheet, PDF (21/48 Pages) Analog Devices – DSP Microcomputer

Programmable Flags Cycle Timing
Table 10 and Figure 9 describe Programmable Flag operations.
Table 10. Programmable Flags Cycle Timing
Parameter
Min
Switching Characteristics
t_DFO
Flag Output Delay with Respect to CLKOUT
t_HFO
Flag Output Hold After CLKOUT High
Timing Requirement
t_HFI
Flag Input Hold is Asynchronous
3
CLKOUT
PF
(OUTPUT)
PF
(INPUT)
t_DFO
t_HFO
FLAG OUTPUT
t_HFI
FLAG INPUT
Figure 9. Programmable Flags Cycle Timing
Timer PWM_OUT Cycle Timing
Table 11 and Figure 10 describe timer expired operations. The
input signal is asynchronous in “width capture mode” and has
an absolute maximum input frequency of 40 MHz.
Table 11. Timer PWM_OUT Cycle Timing
Parameter
Min
Switching Characteristic
t_HTO
Timer Pulsewidth Output¹
12.5
1_{The minimum time for tHTO is one cycle, and the maximum time for tHTO equals (2}32 _{–1) cycles.}
HCLK
PWM_OUT
t_HTO
Figure 10. Timer PWM_OUT Cycle Timing
ADSP-2191M
Max
7
6
Unit
ns
ns
ns
Max
(2³²â€“1) cycles
Unit
ns
REV. A
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