ADSP-BF592KCPZ-2 Datasheet, PDF (4/44 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF592
head looping. The architecture is fully interlocked, meaning that
the programmer need not manage the pipeline when executing
instructions with data dependencies.
The address arithmetic unit provides two addresses for simulta-
neous dual fetches from memory. It contains a multiported
register file consisting of four sets of 32-bit index, modify,
length, and base registers (for circular buffering) and eight
additional 32-bit pointer registers (for C-style indexed stack
manipulation).
Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. At the L1 level, the instruction
memory holds instructions only. Data memory holds data, and
a dedicated scratchpad data memory stores stack and local vari-
able information.
Multiple L1 memory blocks are provided. The memory
management unit (MMU) provides memory protection for
individual tasks that may be operating on the core and can
protect system registers from unintended access.
The architecture provides three modes of operation: user mode,
supervisor mode, and emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while supervisor mode has
unrestricted access to the system and core resources.
The Blackfin processor instruction set has been optimized so
that 16-bit opcodes represent the most frequently used instruc-
tions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, representing
fully featured multifunction instructions. Blackfin processors
support a limited multi-issue capability, where a 32-bit instruc-
tion can be issued in parallel with two 16-bit instructions,
allowing the programmer to use many of the core resources in a
single instruction cycle.
The Blackfin processor assembly language uses an algebraic syn-
tax for ease of coding and readability. The architecture has been
optimized for use in conjunction with the C/C++ compiler,
resulting in fast and efficient software implementations.
ADDRESS ARITHMETIC UNIT
DA1 32
DA0 32
I3 L3 B3
M3
I2 L2 B2
M2
I1 L1 B1
M1
I0 L0 B0
M0
32
RAB
DAG1
DAG0
SP
FP
P5
P4
P3
P2
P1
P0
32
PREG
SD
32
LD1
32
LD0
32
32
32
R7.H
R6.H
R5.H
R4.H
R3.H
R2.H
R1.H
R0.H
R7.L
R6.L
R5.L
R4.L
R3.L
R2.L
R1.L
R0.L
16
8
8
BARREL
SHIFTER
40
16
8
40
A0
40 40
A1
32
32
DATA ARITHMETIC UNIT
Figure 2. Blackfin Processor Core
ASTAT
8
SEQUENCER
ALIGN
DECODE
LOOP BUFFER
CONTROL
UNIT
Rev. B | Page 4 of 44 | July 2013