ADSP-BF592KCPZ-2 Datasheet, PDF (35/44 Pages) Analog Devices – Blackfin Embedded Processor

JTAG Test And Emulation Port Timing
Table 31 and Figure 24 describe JTAG port operations.
Table 31. JTAG Port Timing
Parameter
Min
Timing Requirements
t_TCK
TCK Period
20
t_STAP
TDI, TMS Setup Before TCK High
4
t_HTAP
TDI, TMS Hold After TCK High
4
t_SSYS
System Inputs Setup Before TCK High¹
4
t_HSYS
System Inputs Hold After TCK High¹
5
t_TRSTW
TRST Pulse Width² (measured in TCK cycles)
4
Switching Characteristics
t_DTDO
t_DSYS
TDO Delay from TCK Low
System Outputs Delay After TCK Low³
1 _{System inputs = SCL, SDA, PF15–0, PG15–0, PH2–0, TCK, NMI, BMODE3–0, PG.}
2 _{50 MHz maximum.}
3 _{System outputs = CLKOUT, SCL, SDA, PF15–0, PG15–0, PH2–0, TDO, EMU, EXT_WAKE.}
V_DDEXT
1.8V Nominal
Max
10
13
TCK
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
t_TCK
t_STAP
t_DTDO
t_DSYS
t_SSYS
t_HTAP
t_HSYS
Figure 24. JTAG Port Timing
ADSP-BF592
V_DDEXT
2.5 V/3.3V Nominal
Min
Max
Unit
20
ns
4
ns
4
ns
5
ns
5
ns
4
TCK
10
ns
13
ns
Rev. B | Page 35 of 44 | July 2013