ADSP-BF592KCPZ-2 Datasheet, PDF (24/44 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF592
Parallel Peripheral Interface Timing
Table 20 and Figure 9 through Figure 13 describe parallel
peripheral interface operations.
Table 20. Parallel Peripheral Interface Timing
Parameter
Min
V_DDEXT = 1.8 V
Max
V_DDEXT = 2.5 V/3.3 V
Min
Max
Unit
Timing Requirements
t_PCLKW
PPI_CLK Width¹
t_PCLK
PPI_CLK Period¹
Timing Requirements—GP Input and Frame Capture Modes
t_SCLK – 1.5
t_SCLK – 1.5
ns
2 × t_SCLK – 1.5
2 × t_SCLK – 1.5
ns
t_PSUD
External Frame Sync Startup Delay²
4 × t_PCLK
4 × t_PCLK
ns
t_SFSPE
External Frame Sync Setup Before PPI_CLK
6.7
6.7
ns
(Nonsampling Edge for Rx, Sampling Edge for Tx)
t_HFSPE
External Frame Sync Hold After PPI_CLK
1.8
1.6
ns
t_SDRPE
Receive Data Setup Before PPI_CLK
4.1
3.5
ns
t_HDRPE
Receive Data Hold After PPI_CLK
2
1.6
ns
Switching Characteristics—GP Output and Frame Capture Modes
t_DFSPE
Internal Frame Sync Delay After PPI_CLK
9.0
8.0
ns
t_HOFSPE
t_DDTPE
t_HDTPE
Internal Frame Sync Hold After PPI_CLK
Transmit Data Delay After PPI_CLK
Transmit Data Hold After PPI_CLK
1.7
1.7
ns
8.7
8.0
ns
2.3
1.9
ns
1 _{PPI_CLK frequency cannot exceed fSCLK/2.}
2 _{The PPI port is fully enabled 4 PPI clock cycles after the PAB write to the PPI port enable bit. Only after the PPI port is fully enabled are external frame syncs and data words}
guaranteed to be received correctly by the PPI peripheral.
PPI_CLK
PPI_FS1/2
t_PSUD
Figure 9. PPI with External Frame Sync Timing
PPI_CLK
PPI_FS1/2
PPI_DATA
DATA SAMPLED /
FRAME SYNC SAMPLED
DATA SAMPLED /
FRAME SYNC SAMPLED
t_SFSPE
t_HFSPE
t_PCLKW
t_PCLK
t_SDRPE
t_HDRPE
Figure 10. PPI GP Rx Mode with External Frame Sync Timing
Rev. B | Page 24 of 44 | July 2013