ADSP-BF592KCPZ-2 Datasheet, PDF (19/44 Pages) Analog Devices – Blackfin Embedded Processor

Total Power Dissipation
Total power dissipation has two components:
1. Static, including leakage current
2. Dynamic, due to transistor switching characteristics
Many operating conditions can also affect power dissipation,
including temperature, voltage, operating frequency, and pro-
cessor activity. Electrical Characteristics on Page 18 shows the
current dissipation for internal circuitry (V_DDINT). I_DDDEEPSLEEP
specifies static power dissipation as a function of voltage
(V_DDINT) and temperature (see Table 12), and I_DDINT specifies the
total power specification for the listed test conditions, including
the dynamic component as a function of voltage (V_DDINT) and
frequency (Table 13).
There are two parts to the dynamic component. The first part is
due to transistor switching in the core clock (CCLK) domain.
This part is subject to an Activity Scaling Factor (ASF), which
represents application code running on the processor core and
L1 memories (Table 11).
ADSP-BF592
The ASF is combined with the CCLK frequency and V_DDINT
dependent data in Table 13 to calculate this part. The second
part is due to transistor switching in the system clock (SCLK)
domain, which is included in the I_DDINT specification equation.
Table 11. Activity Scaling Factors (ASF)¹
I_DDINT Power Vector
Activity Scaling Factor (ASF)
I_DD-PEAK
1.29
I_DD-HIGH
1.26
I_DD-TYP
1.00
I_DD-APP
0.83
I_DD-NOP
0.66
I_DD-IDLE
0.33
1 _{See Estimating Power for ASDP-BF534/BF536/BF537 Blackfin Processors}
(EE-297). The power vector information also applies to the ADSP-BF592
processor.
Table 12. Static Current - I_DD-DEEPSLEEP (mA)
T_J (°C)¹
1.15 V
1.20 V
1.25 V
Voltage (V_DDINT)¹
1.30 V
1.35 V
25
0.85
0.98
1.13
1.29
1.46
40
1.57
1.8
2.01
2.16
2.51
55
2.57
2.88
3.2
3.5
3.84
70
4.04
4.45
4.86
5.3
5.81
85
6.52
7.12
7.73
8.36
9.09
100
9.67
10.51
11.37
12.24
13.21
115
14.18
15.29
16.45
17.71
19.05
1 _{Valid temperature and voltage ranges are model-specific. See Operating Conditions on Page 16.}
1.40 V
1.62
2.74
4.22
6.31
9.86
14.26
20.45
1.45 V
1.85
3.05
4.63
6.87
10.67
15.37
21.96
1.50 V
2.07
3.36
5.05
7.45
11.54
16.55
23.56
Table 13. Dynamic Current in CCLK Domain (mA, with ASF = 1.0)¹
f_CCLK
(MHz)²
1.15 V
1.20 V
1.25 V
Voltage (V_DDINT)²
1.30 V
1.35 V
1.40 V
1.45 V
1.50 V
400
N/A
N/A
N/A
N/A
85.31
88.96
92.81
96.63
350
N/A
N/A
N/A
72.08
75.41
78.70
82.07
85.46
300
N/A
57.52
60.38
63.22
66.14
69.02
71.93
75.05
250
46.10
48.43
50.76
53.19
55.68
58.17
60.69
63.23
200
37.86
39.80
41.76
43.79
45.81
47.85
49.97
52.09
100
21.45
22.56
23.78
24.98
25.97
26.64
27.92
29.98
1 _{The values are not guaranteed as stand-alone maximum specifications. They must be combined with static current per the equations of Electrical Characteristics on Page 18.}
2 _{Valid frequency and voltage ranges are model-specific. See Operating Conditions on Page 16 and Table 8 on Page 17.}
Rev. B | Page 19 of 44 | July 2013