ADSP-21365 Datasheet, PDF (38/54 Pages) Analog Devices – SHARC Processor

ADSP-21365/6
SPDIF Receiver
The following sections describe timing as it relates to the SPDIF
receiver.
Internal Digital PLL Mode
In internal Digital Phase-locked Loop mode the internal PLL
(Digital PLL) generates the 512 × Fs clock.
Table 34. SPDIF Receiver Internal Digital PLL Mode Timing
Parameter
Min
Switching Characteristics
t_DFSI
LRCLK Delay After SCLK
t_HOFSI
LRCLK Hold After SCLK
–2
t_DDTI
Transmit Data Delay After SCLK
t_HDTI
Transmit Data Hold After SCLK
–2
t_SCLKIW¹
Transmit SCLK Width
40
t_CCLK
Core Clock Period
1 _{SCLK frequency is 64 x FS where FS = the frequency of LRCLK.}
Preliminary Technical Data
Max
Unit
5
ns
ns
5
ns
ns
ns
5
ns
DRIVE EDGE
DAI_P20-1
(SCLK)
DAI_P20-1
(FS)
DAI_P20-1
(DATA CHANNEL A/B)
t_HOFSI
t_HDTI
t_DFSI
t_SCLKIW
t_SFSI
t_DDTI
SAMPLE EDGE
t_HFSI
Figure 31. SPDIF Receiver Internal Digital PLL Mode Timing
Rev. PrA | Page 38 of 54 | September 2004