ADSP-21365 Datasheet, PDF (34/54 Pages) Analog Devices – SHARC Processor

ADSP-21365/6
Preliminary Technical Data
Sample Rate Converter—Serial Input Port
The SRC input signals (SCLK, FS, and SDATA) are routed from
the DAI_P20–1 pins using the SRU. Therefore, the timing spec-
ifications provided in Table 30 are valid at the DAI_P20–1 pins.
Table 30. SRC, Serial Input Port
Parameter
Min
Max
Unit
Timing Requirements
t_SIFS¹
FS Setup Before SCLK Rising Edge
4
ns
t_SIHFS¹
FS Hold After SCLK Rising Edge
5.5
ns
t_SISD¹
SData Setup Before SCLK Rising Edge
4
ns
t_SIHD¹
SData Hold After SCLK Rising Edge
5.5
ns
t_IDPCLKW
Clock Width
9
ns
t_IDPCLK
Clock Period
20
ns
1 _{DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.}
DAI_P20-1
(SCLK)
DAI_P20-1
(FS)
DAI_P20-1
(SDATA)
t_IDPCLKW
SAMPLE EDGE
t_{S IS F S}
t_SISD
t_SIHFS
t_SIHD
Figure 25. SRC Serial Input Port Timing
Rev. PrA | Page 34 of 54 | September 2004