ADSP-21365 Datasheet, PDF (1/54 Pages) Analog Devices – SHARC Processor

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Preliminary Technical Data
SUMMARY
High performance 32-bit/40-bit floating point processor
optimized for high performance automotive audio
processing
Audio decoder and post processor-algorithm support with
32-bit floating-point implementations
Non-volatile memory may be configured to support audio
decoders and post processor-algorithms like PCM, Dolby
Digital EX, Dolby Prologic IIx, DTS 96/24, Neo:6, DTS ES,
MPEG2 AAC, MPEG2 2channel, MP3, and functions like
Bass management, Delay, Speaker equalization, Graphic
equalization, and more. Decoder/post-processor algo-
rithm combination support will vary depending upon the
chip version and the system configurations. Please visit
www.analog.com/SHARC
SHARC^® Processor
ADSP-21365/ADSP-21366
Single-Instruction Multiple-Data (SIMD) computational
architecture
On-chip memory—3M bit of on-chip SRAM and a dedicated
4M bit of on-chip mask-programmable ROM
Code compatible with all other members of the SHARC family
The ADSP-21365/6 is available with a 333 MHz core instruc-
tion rate and unique audio centric peripherals such as the
Digital Audio Interface, S/PDIF transceiver, DTCP (Digital
Content Transmission Protocol) available on the ADSP-
21365 only, serial ports, 8-channel asynchronous sample
rate converter, precision clock generators and more. For
complete ordering information, see Ordering Guide on
page 51
CORE PROCESSOR
TIMER
INSTRUCTION
CACHE
32 X 48-BIT
DAG1
8X4X32
DAG2
8X4X32
PROGRAM
SEQUENCER
BLOCK 0
SRAM
1M BIT ROM
2M BIT
4 BLOCKS OF ON-CHIP MEMORY
BLOCK 1
BLOCK 2
SRAM
1M BIT ROM
2M BIT
SRAM
0.5M BIT
BLOCK 3
SRAM
0.5M BIT
ADDR DATA
ADDR DATA ADDR DATA ADDR DATA
PM ADDRESS BUS
32
DM ADDRESS BUS 32
PM DATA BUS
64
DM DATA BUS 64
IOA
IOD
IOA
IOD
IOA
IOD
IOA
IOD
PROCESSING
ELEMENT
(PEX)
PROCESSING
ELEMENT
(PEY)
PX REGISTER
6
JTAG TEST & EMULATION
S
IOP REGISTERS
(MEMORY MAPPED)
SPI
SPORTS
IDP
PCG
TIMERS
SRC
SPDIF
DTCP
I/O PROCESSOR
AND PERIPHERALS
SEE “ADSP-21365/6 MEMORY
AND I/O INTERFACE FEATURES”
SECTION FOR DETAILS
SIGNAL
ROUTING
UNIT
Figure 1. Functional Block Diagram – Processor Core
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Rev. PrA
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