ADSP-21365 Datasheet, PDF (33/54 Pages) Analog Devices – SHARC Processor

Preliminary Technical Data
ADSP-21365/6
Parallel Data Acquisition Port (PDAP)
The timing requirements for the PDAP are provided in
Table 29. PDAP is the parallel mode operation of channel 0 of
the IDP. For details on the operation of the IDP, see the IDP
chapter of the ADSP-2136x SHARC Processor Hardware Refer-
ence. Note that the most significant 16 bits of external PDAP
data can be provided through either the parallel port AD15–0 or
the DAI_P20–5 pins. The remaining 4 bits can only be sourced
through DAI_P4–1. The timing below is valid at the
DAI_P20–1 pins or at the AD15–0 pins.
Table 29. Parallel Data Acquisition Port (PDAP)
Parameter
Timing Requirements
t_SPCLKEN¹
PDAP_CLKEN Setup Before PDAP_CLK Sample Edge
t_HPCLKEN¹
PDAP_CLKEN Hold After PDAP_CLK Sample Edge
t_PDSD¹
PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge
t_PDHD¹
PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge
t_PDCLKW
Clock Width
t_PDCLK
Clock Period
Min
Max
Unit
2.5
ns
2.5
ns
2.5
ns
2.5
ns
7
ns
24
ns
Switching Characteristics
t_PDHLDD
Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word 2 × t_CCLK
ns
t_PDSTRB
PDAP Strobe Pulse Width
1 × t_CCLK – 1
ns
1 _{Source pins of DATA are ADDR7–0, DATA7–0, or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.}
DAI_P20-1
(PDAP_CLK)
DAI_P20-1
(PDAP_CLKEN)
DATA
SAMPLE EDGE
t_PDCLKW
t_PDCLK
t_SPCLKEN
t_PDSD
t_HPCLKEN
t_PDHD
DAI_P20-1
(PDAP_STROBE)
t_PDHLDD
Figure 24. PDAP Timing
t_PDSTRB
Rev. PrA | Page 33 of 54 | September 2004