AD9992_15 Datasheet, PDF (36/92 Pages) Analog Devices – 12-Bit CCD Signal Processor with Precision Timing Generator

AD9992
Vertical Masking Using FREEZE/RESUME Registers
As shown in Figure 43 and Figure 44, the FREEZE/RESUME
registers are used to temporarily mask the V-outputs. The pixel
locations to begin the masking (FREEZE) and end the masking
(RESUME) create an area in which the vertical toggle positions
are ignored. At the pixel location specified in the FREEZE register,
the V-outputs are held static at their current dc state, high or low.
The V-outputs are held until the pixel location that is specified
by the RESUME register is reached, at which point the signals
continue with any remaining toggle positions, if any exist.
Four sets of FREEZE/RESUME registers are provided, allowing the
vertical outputs to be interrupted up to four times in the same line.
The FREEZE and RESUME Position 1 to Position 4 are enabled
independently and applied to all groups (Group A, Group B, Group
C, and Group D) using the VMASK_EN register.
Note that when masking is enabled, Group A, Group B, Group C,
and Group D use the same FREEZE/RESUME positions.
Note that the FREEZE/RESUME registers are also used as the
VALTSEL0 and VALTSEL1 registers during special vertical
alternation mode.
HD
XV1
XV24
NO MASKING AREA
Figure 43. No FREEZE/RESUME
HD
V-MASKING AREA
FREEZE
RESUME
XV1
XV24
NOTES
1. ALL TOGGLE POSITIONS WITHIN THE FREEZE/RESUME MASKING AREA ARE IGNORED. H-COUNTER CONTINUES TO COUNT DURING MASKING.
2. FOUR SEPARATE MASKING AREAS ARE AVAILABLE, USING FREEZE1/RESUME1, FREEZE2/RESUME2, FREEZE3/RESUME3, AND
FREEZE4/RESUME4 REGISTERS.
Figure 44. Using FREEZE/RESUME
Rev. C | Page 36 of 92