AD9992_15 Datasheet, PDF (1/92 Pages) Analog Devices – 12-Bit CCD Signal Processor with Precision Timing Generator

12-Bit CCD Signal Processor with
Precision Timing Generator
AD9992
FEATURES
1.8 V AFETG core
Internal LDO regulator and charge pump circuitry
Compatibility with 3 V or 1.8 V systems
24 programmable vertical clock outputs
Correlated double sampler (CDS) with −3 dB, 0 dB,
+3 dB, and +6 dB gain
6 dB to 42 dB, 10-bit variable gain amplifier (VGA)
12-bit, 40 MHz ADC
Black level clamp with variable level control
Complete on-chip timing generator
Precision Timing core with 400 ps resolution
On-chip 3 V horizontal and RG drivers
General-purpose outputs (GPOs) for shutter and
system support
On-chip driver for external crystal
On-chip sync generator with external sync input
105-lead CSP_BGA package, 8 mm × 8 mm, 0.65 mm pitch
APPLICATIONS
Digital still cameras
GENERAL DESCRIPTION
The AD9992 is a highly integrated CCD signal processor for
digital still camera applications. It includes a complete analog
front end with analog to digital conversion combined with
a full-function programmable timing generator. The timing
generator is capable of supporting up to 24 vertical clock signals
to control advanced CCDs. A Precision Timing™ core allows
adjustment of high speed clocks with approximately 400 ps
resolution at 40 MHz operation. The AD9992 also contains
eight general-purpose inputs/outputs that can be used for
shutter and system functions.
The AD9992 is specified at pixel rates of up to 40 MHz. The
analog front end includes black level clamping, CDS, VGA, and
a 12-bit analog-to-digital converter (ADC). The timing generator
provides all the necessary CCD clocks: RG, H-clocks, V-clocks,
sensor gate pulses, substrate clock, and substrate bias control.
Operation is programmed using a 3-wire serial interface.
The AD9992 is specified over an operating temperature range
of −25°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
REFT REFB
CCDIN
CDS
6dB TO 42dB
VGA
VREF
12-BIT
ADC
AD9992
12
DOUT
–3dB, 0dB, +3dB, +6dB
3V INPUT
1.8V OUTPUT
LDO
REG
1.8V INPUT
3V OUTPUT
CHARGE
PUMP
RG
HL
HORIZONTAL
8
DRIVERS
H1 TO H8
24
XV1 TO XV24
XSUBCK
VERTICAL
TIMING
CONTROL
8
CLAMP
INTERNAL CLOCKS
PRECISION
TIMING
GENERATOR
SYNC
GENERATOR
INTERNAL
REGISTERS
SL
SCK
SDATA
GPO1 TO GPO8
HD VD SYNC CLI CLO
Figure 1.
Rev. C
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