AD9992_15 Datasheet, PDF (24/92 Pages) Analog Devices – 12-Bit CCD Signal Processor with Precision Timing Generator

AD9992
HBLK
H1/H3
H2/H4
1/F_PIX
2 × (1/F_PIX)
H-CLOCK FREQUENCY CAN BE REDUCED DURING HBLK BY 1/2 (AS SHOWN),
1/4, 1/6, 1/8, 1/10, 1/12, AND SO ON, UP TO 1/30 USING HBLKWIDTH REGISTER
Figure 28. Generating Wide H-Clock Pulses During HBLK Interval
HD
CREATE UP TO 3 GROUPS OF TOGGLES
A, B, C COMMON IN ALL REPEAT AREAS _{MASK A, B, C PULSES IN ANY REPEAT CHANGE NUMBER OF A, B, C PULSES IN ANY}
A
AREA BY SETTING RA*H*REP* = 0 REPEAT AREA USING RA*H*REP* REGISTERS
B
C
H1
H2
REPEAT AREA 0 REPEAT AREA 1 REPEAT AREA 2 REPEAT AREA 3 REPEAT AREA 4 REPEAT AREA 5
HBLKSTART
Figure 29. HBLK Mode 2 Operation
HBLKEND
HD
HBLK
H1
H2
HBLKLEN
HBLKSTARTA
HBLKSTARTB
ALL RA*H*REPA/B/C REGISTERS = 2 TO CREATE TWO HCLK PULSES
HBLKSTARTC
RA0H1REPA RA0H1REPB RA0H1REPC
RA1H1REPA RA1H1REPB RA1H1REPC
HBLKSTART
RA0H2REPA RA0H2REPB RA0H2REPC
RA1H2REPA RA1H2REPB RA1H2REPC
REPEAT AREA 0
REPEAT AREA 1
HBLKREP = 2
TO CREATE TWO REPEAT AREAS
Figure 30. HBLK Mode 2 Registers
HBLKEND
Rev. C | Page 24 of 92