EVAL-ADF4113EBZ1 Datasheet, PDF (27/28 Pages) Analog Devices – RF PLL Frequency Synthesizers

Data Sheet
ADF4110/ADF4111/ADF4112/ADF4113
OUTLINE DIMENSIONS
PIN 1
INDICATOR
0.80
0.75
0.70
SEATING
PLANE
4.10
4.00 SQ
3.90
TOP VIEW
0.50
BSC
0.30
0.25
0.18
16
15
20
1
EXPOSED
PAD
PIN 1
INDICATOR
2.30
2.10 SQ
2.00
11
5
0.65
0.60
10
6
BOTTOM VIEW
0.20 MIN
0.55
0.05 MAX
0.02 NOM
COPLANARITY
0.08
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-1.
Figure 40. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-20-6)
Dimensions shown in millimeters
5.10
5.00
4.90
16
9
4.50
4.40
4.30
1
6.40
BSC
8
PIN 1
1.20
0.15
MAX
0.20
0.05
0.09
0.75
0.30
8°
0.60
0.65
BSC
0.19 SEATING
PLANE
0°
0.45
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 41. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
Rev. F | Page 27 of 28