ADSP-21160N Datasheet, PDF (26/53 Pages) Analog Devices – DSP Microcomputer

PRELIMINARY TECHNICAL DATA
April 2002
For current information contact Analog Devices at 800/262-5643
ADSP-21160N
Memory Write—Bus Master
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-21160N is the bus master accessing external memory space in asyn-
chronous access mode. Note that timing for ACK, DATA, RDx, WRx, and DMAG strobe timing parameters only applies
to asynchronous access mode.
Table 11. Memory Write—Bus Master
Parameter
Min
Max
Unit
Timing Requirements:
t_DAAK
t_DSAK
t_SAKC
t_HAKC
ACK Delay from Address, Selects^1,2
ACK Delay from WRx Low^1,3
ACK Setup to CLKIN^1,3
ACK Hold After CLKIN^1,3
Switching Characteristics:
0.5t_CCLK + 3
1
t_CK – 0.5t_CCLK– 12 + W
ns
t_CK – 0.75t_CCLK – 11 + W ns
ns
ns
t_DAWH
t_DAWL
t_WW
t_DDWH
t_DWHA
t_DWHD
t_DATRWH
t_WWR
t_DDWR
t_WDE
Address, CIF, Selects to WRx
t_CK – 0.25t_CCLK – 3 + W
ns
Deasserted^2,3
Address, CIF, Selects to WRx Low²
0.25t_CCLK – 3
ns
WRx Pulse width³
t_CK – 0.5t_CCLK – 1 + W
ns
Data Setup before WRx High³
t_CK – 0.5t_CCLK – 1 + W
ns
Address Hold after WRx Deasserted³ 0.25t_CCLK – 1+ H
ns
Data Hold after WRx Deasserted³
0.25t_CCLK – 1 + H
ns
Data Disable after WRx Deasserted^3,4 0.25t_CCLK – 2 + H
0.25t_CCLK+ 2 + H
ns
WRx High to WRx, RDx, DMAGx Low³ 0.5t_CCLK – 1+HI
ns
Data Disable before WRx or RDx Low 0.25t_CCLK – 1+ I
ns
WRx Low to Data Enabled
–0.25t_CCLK – 1
ns
W = (number of wait states specified in WAIT register) × t_CK.
H = t_CK (if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
HI = t_CK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
I = t_CK (if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
1_{ACK Delay/Setup: User must meet tDAAK or tDSAK or tSAKC for deassertion of ACK (Low), all three specifications must be met for assertion of ACK (High).}
2_{The falling edge of MSx, BMS is referenced.}
3_{Note that timing for ACK, DATA, RDx, WRx, and DMAG strobe timing parameters only applies to asynchronous access mode.}
4_{See Example System Hold Time Calculation on page 47 for calculation of hold times given capacitive and dc loads.}
ADDRESS
MSx , BMS ,
CIF
WRx
DATA
ACK
CLKIN
t_DAWL
t_WDE
t_DAWH
t_WW
t_DDWH
t_DAAK
t_DSAK
t_SAKC
t_HAKC
t_DWHA
t_DATRWH
t_WWR
t_DDWR
t_DWHD
RDx
DMAG
Figure 18. Memory Write—Bus Master
REV. PrB ^{This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog}
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