HMC6301 Datasheet, PDF (12/24 Pages) Analog Devices – Programmable baseband gain and filter bandwidth

HMC6301
THEORY OF OPERATION
An integrated frequency synthesizer creates a low phase noise
LO between 16.3 GHz and 18.3 GHz. The step size of the
synthesizer equates to 250 MHz steps at RF when used with a
71.42857 MHz reference crystal or to 500 MHz if used with a
142.857 reference crystal. To support IEEE channels (ISM band)
with a 540 MHz step size, use a 154.2857 MHz reference crystal.
A 57 GHz to 64 GHz signal enters the chip through a single-
ended LNA input. The LNA provides 20 dB of variable gain.
The LO is multiplied by three and mixed with the LNA output
to downconvert to an 8.14 GHz to 9.1 GHz sliding IF. An
integrated notch filter removes the image frequency at 40 GHz
to 46 GHz. The IF signal is filtered and amplified with 14 dB of
variable gain. If the chip is configured for I/Q baseband output,
the IF signal feds into a quadrature demodulator using the LO/2
to downconvert to baseband. There are also options to use on-
chip demodulators capable of demodulating AM/FM/FSK/MSK
waveforms.
The phase noise and quadrature balance of the on-chip synthesizer
is sufficient to support up to 64 QAM modulation. For higher
order modulation up to 256 QAM or less than a 250 MHz step
size, the HMC6301 can operate using an external LO.
The HMC6301 receiver is ideal for FDD operation along with
the HMC6300 transmitter chip. However, both devices can
support TDD operation by enabling and disabling the circuits.
All of the enables are placed in Register Array 4, allowing full
chip enable or disable in one SPI write.
There are no special power sequencing requirements for the
HMC6301; apply all voltages simultaneously.
TIME = 0
ENABLE
Data Sheet
REGISTER ARRAY ASSIGNMENT AND SERIAL
INTERFACE
The register arrays for both the receiver and transmitter are
organized into 32 rows of 8 bits. Using the serial interface, the
arrays are written to or read from one row at a time, as shown in
Figure 17 and Figure 18, respectively. Figure 17 shows the
sequence of signals on the ENABLE, CLK, and DATA lines to
write one 8-bit row of the register array. The ENABLE line goes
low, the first of 18 data bits (Bit 0) is placed on the DATA line,
and 2 ns or more after the DATA line stabilizes, the CLK line
goes high to clock in Data Bit 0. The DATA line must remain
stable for at least 2 ns after the rising edge of CLK.
A write operation requires 18 data bits and 18 clock pulses, as
shown in Figure 17. The 18 data bits contain the 8-bit register
array row data (the least significant bit (LSB) is clocked in first),
followed by the register array row address (ROW0 through
ROW23, 000000 to 001111, LSB first), the read/write bit (set to
1 to write), and finally, the receiver chip address, 111, LSB first).
The receiver IC serial interface was tested to 500 MHz, and the
interface is 1.2 V CMOS levels.
Note that the register array row address is 6 bits but only four
are used to designate 32 rows, the two most significant bits
(MSBs) are 0.
After the 18th clock pulse of the write operation, the ENABLE
line returns high to load the register array on the IC; prior to
the rising edge of the ENABLE line, no data is written to the
array. The CLK line should have stabilized in the low state at
least 2 ns prior to the rising edge of the ENABLE line.
1
18
CLK
DATA
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
LSB
DATA
MSB LSB
ARRAY ADDRESS
MSB
CHIP
ADDRESS
LSB
MSB
R/W = 1
Figure 17. Timing Diagram for Writing a Row of the Receiver Serial Interface
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