OP215 Datasheet, PDF (1/8 Pages) Analog Devices – Dual Precision JFET-Input Operational Amplifier

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FEATURES
High Slew Rate: 10 V/␮s Min
Fast Settling Time: 0.9 ␮s to 0.1% Type
Low Input Offset Voltage Drift: 10 ␮V/؇C Max
Wide Bandwidth: 3.5 MHz Min
Temperature-Compensated Input Bias Currents
Guaranteed Input Bias Current: 18 nA Max (125؇C)
Bias Current Specified Warmed Up over Temperature
Low Input Noise Current: 0.01 pA/÷Hz Type
High Common-Mode Rejection Ratio 86 dB Min
Pin Compatible with Standard Dual Pinouts
Models with MIL-STD-883 Class B Processing Available
Dual Precision JFET-Input
Operational Amplifier
OP215
GENERAL DESCRIPTION
The OP215 offers the proven JFET-input performance advantages
of high speed and low input bias current with the tracking and
convenience advantages of a dual op amp configuration.
Low input offset voltages, low input currents, and low drift are
featured in these high-speed amplifiers.
On-chip zener-zap trimming is used to achieve low V_OS, while a
bias-current compensation scheme gives a low input bias current
at elevated temperature. Thus, the OP215 features an input bias
current of 1.4 nA at 70∞C ambient (not junction) temperature
which greatly extends the application usefulness of this device.
Applications include high-speed amplifiers for current output
DACs, active filters, sample-and-hold buffers, and photocell
amplifiers. For additional precision JFET op amps, see the
OP249 and AD712 data sheets.
V+
NOMINV
INPUT+
V–
Q5
J5
Q6 ^NULL
R1
J1
J2
Q7
R3
Q8
–INV J11
INPUT
Q12
C1
J3
J4
7.4
pF
R8
J8 J7
Q11
R9
R4
R7
NULL
Q10
Q9
J6
NOTE
R7, R8 ARE ELECTRONICALLY ADJUSTED
ON-CHIP FOR MINIMUM OFFSET VOLTAGE
Q19
Q24
Q1
Q3
R5
3.6
k⍀ ^Q13
Q16
R2 ^C2
7.4pF
Q2
Q4
R6
3.6k⍀
Q15
Q17
R13
Q18
J10
Q23
Q14
J9
Q20
Q21
R11
Q22
OUTPUT
R10
Q25
R12
Figure 1. Simplified Schematic (1/2 OP215)
REV. A
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© Analog Devices, Inc., 2002