M7AFS600-1FGG256I Datasheet, PDF (95/318 Pages) Actel Corporation – Actel Fusion Mixed-Signal FPGAs

Actel Fusion Mixed-Signal FPGAs
Timing Characteristics
Table 2-35 • FIFO
Worst Commercial-Case Conditions: T_J = 70°C, V_CC = 1.425 V
Parameter
Description
–2
–1
Std.
Units
t_ENS
t_ENH
t_BKS
t_BKH
t_DS
t_DH
t_CKQ1
t_CKQ2
t_RCKEF
t_WCKFF
t_CKAF
t_RSTFG
t_RSTAF
t_RSTBQ
REN_B, WEN_B Setup time
1.34
1.52
1.79
ns
REN_B, WEN_B Hold time
0.00
0.00
0.00
ns
BLK_B Setup time
0.19
0.22
0.26
ns
BLK_B Hold time
0.00
0.00
0.00
ns
Input data (DI) Setup time
0.18
0.21
0.25
ns
Input data (DI) Hold time
0.00
0.00
0.00
ns
Clock High to New Data Valid on DO (flow-through) 2.17
2.47
2.90
ns
Clock High to New Data Valid on DO (pipelined)
0.94
1.07
1.26
ns
RCLK High to Empty Flag Valid
1.72
1.96
2.30
ns
WCLK High to Full Flag Valid
1.63
1.86
2.18
ns
Clock High to Almost Empty/Full Flag Valid
6.19
7.05
8.29
ns
RESET_B Low to Empty/Full Flag Valid
1.69
1.93
2.27
ns
RESET_B Low to Almost-Empty/Full Flag Valid
6.13
6.98
8.20
ns
RESET_B Low to Data out Low on DO (flow-through) 0.92
1.05
1.23
ns
RESET_B Low to Data out Low on DO (pipelined)
0.92
1.05
1.23
ns
t_REMRSTB
RESET_B Removal
0.29
0.33
0.38
ns
t_RECRSTB
RESET_B Recovery
1.50
1.71
2.01
ns
t_MPWRSTB
RESET_B Minimum Pulse Width
0.21
0.24
0.29
ns
t_CYC
Clock Cycle time
3.23
3.68
4.32
ns
F_MAX
Maximum Frequency for FIFO
310
272
231
ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-7 on page 3-9 for derating
values.
Preliminary v1.7
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