M7AFS600-1FGG256I Datasheet, PDF (124/318 Pages) Actel Corporation – Actel Fusion Mixed-Signal FPGAs

Device Architecture
SYSCLK
ADCSTART
MODE[3:0]
TVC[7:0]
STC[7:0]
VAREF
CHNUMBER[7:0]
t_MINSYSCLK
t_SUADCSTART t_HDADCSTART
t_SUMODE t_HDMODE
t_SUTVC t_HDTVC
t_SUSTC t_HDSTC
t_SUVAREFSEL t_HDVAREFSEL
t_SUCHNUM t_HDCHNUM
Figure 2-82 • Input Setup Time
t_MPWSYSCLK
SYSCLK
ADCSTART
BUSY
SAMPLE
DATAVALID
t_SAMPLE1
t t _{SUADCSTART HDADCSTART}
t_{C K 2 QBU SY}
t_{C K 2 QSAM PL E}
t_CONV2
ADC_RESULT[11:0]
t_DATA2START ³
t_CK2QVAL
t_CK2QVAL
t_{C LK 2R ESU LT}
1^st Sample Result
2^nd Sample Result
Notes:
1. Refer to EQ 2-12 on page 2-104 for the calculation on the sample time, t_SAMPLE.
2. See EQ 2-19 on page 2-106 for calculation on the conversion time, t_CONV.
3. Minimum time to issue an ADCSTART after DATAVALID is 1 SYSCLK period
Figure 2-83 • Standard Conversion Status Signal Timing Diagram
2-108
Preliminary v1.7