M7AFS600-1FGG256I Datasheet, PDF (24/318 Pages) Actel Corporation – Actel Fusion Mixed-Signal FPGAs

Device Architecture
Sequential Timing Characteristics
Table 2-2 •
Parameter
Register Delays
Commercial-Case Conditions: T_J = 70°C, Worst-Case V_CC = 1.425 V
Description
–2
–1 Std. Units
t_CLKQ
Clock-to-Q of the Core Register
0.55 0.63 0.74 ns
t_SUD
Data Setup Time for the Core Register
0.43 0.49 0.57 ns
t_HD
Data Hold Time for the Core Register
0.00 0.00 0.00 ns
t_SUE
Enable Setup Time for the Core Register
0.45 0.52 0.61 ns
t_HE
Enable Hold Time for the Core Register
0.00 0.00 0.00 ns
t_CLR2Q
Asynchronous Clear-to-Q of the Core Register
0.40 0.45 0.53 ns
t_PRE2Q
Asynchronous Preset-to-Q of the Core Register
0.40 0.45 0.53 ns
t_REMCLR
Asynchronous Clear Removal Time for the Core Register
0.00 0.00 0.00 ns
t_RECCLR
Asynchronous Clear Recovery Time for the Core Register
0.22 0.25 0.30 ns
t_REMPRE
Asynchronous Preset Removal Time for the Core Register
0.00 0.00 0.00 ns
t_RECPRE
Asynchronous Preset Recovery Time for the Core Register
0.22 0.25 0.30 ns
t_WCLR
Asynchronous Clear Minimum Pulse Width for the Core Register 0.22 0.25 0.30 ns
t_WPRE
Asynchronous Preset Minimum Pulse Width for the Core Register 0.22 0.25 0.30 ns
t_CKMPWH Clock Minimum Pulse Width HIGH for the Core Register
0.32 0.37 0.43 ns
t_CKMPWL Clock Minimum Pulse Width LOW for the Core Register
0.36 0.41 0.48 ns
Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on
page 3-9.
2-8
Preliminary v1.7