M7AFS600-1FGG256I Datasheet, PDF (54/318 Pages) Actel Corporation – Actel Fusion Mixed-Signal FPGAs

Device Architecture
Crystal Oscillator (Xtal Osc)
When used as the clock source for the RTC, the crystal oscillator will be configured by the RTC with
the RTCXTLMODE[1:0] RTC macro pins. Refer to the "Crystal Oscillator" section on page 2-22 for
specific details on crystal oscillator operation.
The crystal oscillator input to the RTC is divided by 128, so bit 0 of the RTC toggles at the frequency
of the crystal oscillator divided by 128. The frequencies of the RTC are gated by those of the crystal
oscillator, from 32.768 kHz to 20 MHz. When used with a 32.768 kHz crystal, bit 0 of the of RTC has
a period of ~7.8 ms, and bit 7 has a period of 1 second.
Voltage Regulator (VR) Initialization (Init)
The VR Init block determines voltage regulator behavior when the 3.3 V supply is valid. The Fusion
devices support different use models. Some of these require the 1.5 V voltage regulator to turn on
when the 3.3 V supply is stable. Other use models require additional conditions to be met before
the 1.5 V VR turns on. Since the FPGA is not operating when the 3.3 V supply is off, the VR Init
block lets the user define VR behavior at design time. Two bits can be set within the core, which
bits the VR Init block will read as it comes out of reset and either turn on the VR or leave it in an off
state.
Voltage Regulator Logic
The VR Logic block, along with the VR, combines commands from the FPGA, RTC, VR Init block,
V_CC33UP detector, and PUB pad to determine whether or not the VR is enabled.
The VR can be enabled from several sources: the PUB pin, the RTC_MATCH signal from the RTC
block, or triggered by the VR Init block. Once triggered, the VR will remain on. Only the FPGA
fabric can disable the VR, unless the V_CC33A supply falls below the V_CC33UP threshold and a reset
occurs.
2-38
Preliminary v1.7