RTAX-S Datasheet, PDF (88/170 Pages) Actel Corporation – RTAX-S/SL RadTolerant FPGAs

RTAX-S/SL RadTolerant FPGAs
Table 2-89 • Eight RAM Blocks Are Cascaded (Worst-Case Military Conditions V_CCA = 1.4 V, V_CCI = 3.0 V, T_J = 125°C)
'–1' Speed
'Std' Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Write Mode
t_WDASU
Write Data Setup vs. WCLK
7.73
9.09
ns
t_WDAHD
Write Data Hold vs. WCLK
0.30
0.35
ns
t_WADSU
Write Address Setup vs. WCLK
7.73
9.09
ns
t_WADHD
Write Address Hold vs. WCLK
0.30
0.35
ns
t_WENSU
Write Enable Setup vs. WCLK
7.73
9.09
ns
t_WENHD
Write Enable Hold vs. WCLK
0.30
0.35
ns
t_WCKH
WCLK Minimum High Pulse Width
1.31
1.54
ns
t_WCLKL
WCLK Minimum Low Pulse Width
8.94
10.51
ns
t_WCKP
WCLK Minimum Period
17.87
21.01
ns
Read Mode
t_RADSU
t_RADHD
t_RENSU
t_RENHD
t_RCK2RD1
t_RCK2RD2
t_RCLKH
t_RCLKL
t_RCKP
Read Address Setup vs. RCLK
Read Address Hold vs. RCLK
Read Enable Setup vs. RCLK
Read Enable Hold vs. RCLK
RCLK-To-OUT (Pipelined)
RCLK-To-OUT (Non-Pipelined)
RCLK Minimum High Pulse Width
RCLK Minimum Low Pulse Width
RCLK Minimum Period
9.04
10.63
ns
0.00
0.00
ns
9.04
10.63
ns
0.00
0.00
ns
4.77
5.61
ns
7.33
8.62
ns
1.27
1.49
ns
10.05
11.82
ns
20.10
23.63
ns
2-70
v5.3