RTAX-S Datasheet, PDF (64/170 Pages) Actel Corporation – RTAX-S/SL RadTolerant FPGAs

RTAX-S/SL RadTolerant FPGAs
Carry-Chain Logic
The RTAX-S/SL dedicated carry-chain logic offers a very
compact solution for implementing arithmetic functions
without sacrificing performance.
To implement the carry-chain logic, two C-cells in a
Cluster are connected together so the FCO (i.e., carry
out) for the two bits is generated in a Carry Look-ahead
scheme to achieve minimum propagation delay from the
FCI (i.e., carry in) into the two-bit Cluster. The two-bit
carry logic is shown in Figure 2-30.
The FCI of one C-cell pair is driven by the FCO of the
C-cell pair immediately above it. Similarly, the FCO of one
C-cell pair, drives the FCI input of the C-cell pair
immediately below it (Figure 1-5 on page 1-3 and
Figure 2-31 on page 2-47).
The carry-chain logic is selected via the CFN input. When
carry logic is not required, this signal is deasserted to
save power. Again, this configuration is handled
automatically for the user through the Actel macro
library.
The signal propagation delay between two C-cells in the
carry-chain sequence is 0.1 ns.
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DCOUT
Figure 2-30 • RTAX-S/SL Two-Bit Carry Logic
0
10
1
2-46
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