RTAX-S Datasheet, PDF (49/170 Pages) Actel Corporation – RTAX-S/SL RadTolerant FPGAs

RTAX-S/SL RadTolerant FPGAs
1.8 V LVCMOS
Low-Voltage Complementary Metal-Oxide Semiconductor for 1.8 V is an extension of the LVCMOS standard (JESD8-5)
used for general-purpose 1.8 V applications. It uses a 3.3 V tolerant CMOS input buffer and a push-pull output buffer.
Table 2-26 • DC Input and Output Levels
V_IL
Min,V
Max,V
V_IH
Min,V
–0.3
0.2V_CCI
0.7V_CCI
Max,V
2.1
V_OL
Max,V
0.2
V_OH
Min,V
V_CCI-0.2
I_OL
mA
8mA
I_OH
mA
–8mA
AC Loadings
Test Point
for t_pd
Figure 2-17 • AC Test Loads
35 pF
R=1 k
Test Point
for tristate
R to V_CCI for t_plz/t_pzl
R to GND for t_phz/t_pzh
35 pF for t_pzh/t_pzl
5 pF for t_phz^/t_plz
Table 2-27 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V) Input High (V)
0
1.8
Note: *Measuring Point = V_trip
Measuring Point* (V)
0.5V_CCI
V_REF (typ) (V)
N/A
C_load (pF)
35
Timing Characteristics
Table 2-28 • Worst-Case Military Conditions V_CCA = 1.4 V, V_CCI = 1.7 V, T_J = 125°C
'–1' Speed
Parameter
Description
Min. Max.
LVCMOS18 I/O Module Timing
t_DP
t_PY
t_ICLKQ
t_OCLKQ
t_SUD
t_SUE
t_HD
t_HE
t_CPWHL
t_CPWLH
t_WASYN
t_REASYN
t_HASYN
t_CLR
t_PRESET
Input buffer
Output buffer
Clock-to-Q for the I/O input register
Clock-to-Q for the IO output register and the I/O enable register
Data input setup
Enable input setup
Data input hold
Enable input hold
Clock pulse width High to Low
Clock pulse width Low to High
Asynchronous pulse width
Asynchronous recovery time
Asynchronous removal time
Asynchronous Clear-to-Q
Asynchronous Preset-to-Q
3.57
4.97
0.91
0.91
0.31
0.35
0.00
0.00
0.39
0.37
0.37
0.17
0.00
0.31
0.31
'Std.' Speed
Min. Max.
4.19
5.85
1.07
1.07
0.37
0.41
0.00
0.00
0.39
0.37
0.37
0.21
0.00
0.37
0.37
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
v5.3
2-31