A1020B-PG84M Datasheet, PDF (51/98 Pages) Actel Corporation – HiRel FPGAs

HiRel FPGAs
A32100DX Timing Characteristics (continued)
(Worst-Case Military Conditions, V_CC = 4.5V, T_J = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter Description
Min.
Max.
Min.
Max.
Units
TTL Output Module Timing¹
t_DLH
Data to Pad High
5.1
6.8
ns
t_DHL
Data to Pad Low
6.3
8.3
ns
t_ENZH
Enable Pad Z to High
6.6
8.8
ns
t_ENZL
Enable Pad Z to Low
7.1
9.4
ns
t_ENHZ
Enable Pad High to Z
11.5
15.3
ns
t_ENLZ
Enable Pad Low to Z
11.5
15.3
ns
t_GLH
G to Pad High
11.5
15.3
ns
t_GHL
G to Pad Low
12.4
16.6
ns
t_LSU
I/O Latch Output Setup
0.4
0.5
ns
t_LH
I/O Latch Output Hold
0.0
0.0
ns
t_LCO
I/O Latch Clock-Out (Pad-to-Pad) 32 I/O
11.5
15.4
ns
t_ACO
Array Latch Clock-Out (Pad-to-Pad) 32 I/O
16.3
21.7
ns
d_TLH
Capacitive Loading, Low to High
0.04
0.06
ns/pF
d_THL
Capacitive Loading, High to Low
0.06
0.08
ns/pF
t_WDO
Hard-Wired Wide Decode Output
CMOS Output Module Timing¹
0.05
0.07
ns
t_DLH
Data to Pad High
6.3
8.3
ns
t_DHL
Data to Pad Low
5.1
6.8
ns
t_ENZH
Enable Pad Z to High
6.6
8.8
ns
t_ENZL
Enable Pad Z to Low
7.1
9.4
ns
t_ENHZ
Enable Pad High to Z
11.5
15.3
ns
t_ENLZ
Enable Pad Low to Z
11.5
15.3
ns
t_GLH
G to Pad High
11.5
15.3
ns
t_GHL
G to Pad Low
12.4
16.6
ns
t_LSU
I/O Latch Setup
0.4
0.5
ns
t_LH
I/O Latch Hold
0.0
0.0
ns
t_LCO
I/O Latch Clock-Out (Pad-to-Pad) 32 I/O
13.7
18.2
ns
t_ACO
Array Latch Clock-Out (Pad-to-Pad) 32 I/O
19.2
25.6
ns
d_TLH
Capacitive Loading, Low to High
0.06
0.08
ns/pF
d_THL
Capacitive Loading, High to Low
0.05
0.07
ns/pF
t_WDO
Hard-Wired Wide Decode Output
0.05
0.07
ns
Notes:
1. Delays based on 35 pF loading.
2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at
http://www.actel.com/appnotes.
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