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A1020B-PG84M Datasheet, PDF (15/98 Pages) Actel Corporation – HiRel FPGAs | |||
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HiRel FPGAs
3200DX Timing Model (Logic Functions using Quadrant Clocks)*
Input Delays
Internal Delays
I/O Module
tINPY = 1.9 ns
tIRD1 = 2.2 ns
Combinatorial
Module
DQ
tPD = 3.1 ns
G
tINH = 0.0 ns
tINSU = 0.7 ns
tINGO = 4.0 ns
Decode
Module
tPDD = 3.3 ns
Predicted
Routing
Delays
Output Delays
I/O Module
tRD1 = 1.3 ns
tRD2 = 1.9 ns
tRD4 = 3.3 ns
tDLH = 6.3 ns
tRDD = 0.5 ns
QUADRANT
CLOCKS
tCKH = 12 ns**
FMAX = 100 MHz
Sequential
Logic Module
I/O Module
tDLH = 6.3 ns
Combin-
atorial
Logic
included
in tSUD
tSU = 0.5 ns
tHD = 0.0 ns
D Q tRD1 = 1.3 ns
tCO = 3.1 ns
DQ
G
tENHZ = 11.5 ns
tLH = 0.0 ns
tLSU = 0.4 ns
tGHL= 12.4 ns
* Values shown for A32100DXâ1 at worst-case military conditions.
** Load dependent.
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