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A1020B-PG84M Datasheet, PDF (22/98 Pages) Actel Corporation – HiRel FPGAs | |||
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Decode Module Timing
A
B
C
D
E
Y
F
H
G
AâG, H
Y
50%
VCC
VCC
tPLH
SRAM Timing Characteristics
Write Port
WRAD [5:0]
BLKEN
WEN
WCLK
WD [7:0]
RAM Array
32x8 or 64x4
(256 bits)
tPHL
Read Port
RDAD [5:0]
LEW
REN
RCLK
RD [7:0]
22
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