A1020B-PG84M Datasheet, PDF (32/98 Pages) Actel Corporation – HiRel FPGAs

A1280A Timing Characteristics (continued)
(Worst-Case Military Conditions, V_CC = 4.5V, T_J = 125°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
TTL Output Module Timing¹
t_DLH
Data to Pad High
t_DHL
Data to Pad Low
t_ENZH
Enable Pad Z to High
t_ENZL
Enable Pad Z to Low
t_ENHZ
Enable Pad High to Z
t_ENLZ
Enable Pad Low to Z
t_GLH
G to Pad High
t_GHL
G to Pad Low
d_TLH
Delta Low to High
d_THL
Delta High to Low
CMOS Output Module Timing¹
11.0
13.0
ns
13.9
16.4
ns
12.3
14.4
ns
16.1
19.0
ns
9.8
11.5
ns
11.5
13.6
ns
12.4
14.6
ns
15.5
18.2
ns
0.09
0.11
ns/pF
0.17
0.20
ns/pF
t_DLH
Data to Pad High
14.0
16.5
ns
t_DHL
Data to Pad Low
11.7
13.7
ns
t_ENZH
Enable Pad Z to High
12.3
14.4
ns
t_ENZL
Enable Pad Z to Low
16.1
19.0
ns
t_ENHZ
Enable Pad High to Z
9.8
11.5
ns
t_ENLZ
Enable Pad Low to Z
11.5
13.6
ns
t_GLH
G to Pad High
12.4
14.6
ns
t_GHL
G to Pad Low
15.5
18.2
ns
d_TLH
Delta Low to High
0.17
0.20
ns/pF
d_THL
Delta High to Low
0.12
0.15
ns/pF
Notes:
1. Delays based on 50 pF loading.
2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at
http://www.actel.com/appnotes.
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