COREAI-XX Datasheet, PDF (4/25 Pages) Actel Corporation – CoreAI

CoreAI
I/O Signal Descriptions
The port signals for the CoreAI macro are defined in Table 3 and illustrated in Figure 3. CoreAI has 120 I/O signals.
Note that vector notation is used in Figure 3 for the AV, AC, AT, ATRETURN, DDGDON, DAVOUT, DACOUT, DATOUT,
AG, and RTCXTLMODE ports; however, these ports are actually split into individual single-bit ports, as described in
Table 3. For example, there are two individual output ports, RTCXTLMODE1 and RTCXTLMODE0, rather than one
vectored output port RTCXTLMODE[1:0].
PCLK
PRESETN
PADDR[4:0]
PSEL
PENABLE
PWRITE
PWDATA[7:0]
VAREF
GNDREF
AV[9:0]
AC[9:0]
AT[9:0]
ATRETURN[4:0]
DDGDON[9:0]
RTCCLK
PRDATA[7:0]
INTERRUPT
DAVOUT[9:0]
DACOUT[9:0]
DATOUT[9:0]
AG[9:0]
RTCXTLMODE[1:0]
RTCXTLSEL
RTCMATCH
RTCPSMMATCH
Figure 3 • CoreAI I/O Signal Diagram
Table 3 • CoreAI I/O Signal Descriptions
Name
Type Description
APB Interface
PCLK
Input APB System Clock: reference clock for all internal logic
PRESETN
Input APB active-low asynchronous reset
PADDR[4:0]
Input APB address bus – This port is used to address internal CoreAI registers.
PSEL
Input APB Slave Select – This signal selects CoreAI for reads or writes.
PENABLE
Input APB Strobe – This signal indicates the second cycle of an APB transfer.
PWRITE
Input APB Write/Read – If high, a write will occur when an APB transfer to CoreAI takes place; if
low, a read from CoreAI will take place.
PWDATA[15:0]
Input
APB write data – If the APB_16BIT_DATA parameter/generic is set to 1, all 16 bits are used; if
the APB_16BIT_DATA parameter/generic is set to 0, only the lower 8 bits, PWDATA[7:0], are
used (in this case, PWDATA[15:8] should be tied to static high or low values).
PRDATA[15:0]
Output APB read data – If the APB_16BIT_DATA parameter/generic is set to 1, all 16 bits are used; if
the APB_16BIT_DATA parameter/generic is set to 0, only the lower 8 bits, PRDATA[7:0], are
used (in this case, PRDATA[15:8] can be left unconnected).
INTERRUPT
Output Microprocessor interrupt output – This interrupt signal is generated from 14 possible
interrupt sources, each of which can be masked or enabled via the INTENABLE register. The
polarity of this output is controlled via the ACTLOW_INTERRUPT parameter/generic.
Note: All signals active high (logic 1) unless otherwise noted.
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