COREAI-XX Datasheet, PDF (21/25 Pages) Actel Corporation – CoreAI

CoreAI
RTC Operation
For detailed data on the connection and operation of
the 40-bit real-time counter block within the AB macro,
refer to the Fusion datasheet.
The SmartGen software can be used to configure the
RTC. The internal registers of the RTC are accessed via the
ACM interface address map listed in Table 32 on page 18.
Control of the RTC is primarily accomplished via writes to
the RTC CTRL_STAT (Control/Status) register at ACM
address 0x58 (88), which is listed in Table 33. Status
information is primarily obtained by reading the same
register.
Table 33 • RTC Control/Status Register
Bits
Name
Function
7
rtc_rst
RTC Reset: Writing logic 1 to this bit causes an RTC reset.¹ Writing logic 0 to this bit will allow
synchronous removal of reset after two ACM_CLK cycles if VCC33UP = 1.²
6
cntr_en
Counter Enable: Writing logic 1 to this bit will enable the counter if the RTC is not in reset. After
reset is removed and cntr_en = 1, 64 RTCCLK positive edges (one-half of the pre-scaler division
factor) will elapse before the counter is incremented.³ A logic 0 in this bit resets the pre-scaler and
therefore suspends incrementing the counter, but the counter is not reset. Before writing to the
COUNTER registers, the counter must be disabled.
5
vr_en_mat
Voltage Regulator Enable on Match: Writing logic 1 to this bit will allow the RTCMATCH output
port to transition to logic 1 when a match occurs between the 40-bit counter and the 40-bit match
register. Logic 0 forces RTCMATCH to logic 0 to prevent enabling the voltage regulator from the
RTC.
4:3
xt_mode[1:0]
Crystal Oscillator Mode: These bits control the RTCXTLMODE[1:0] output ports that are connected
to the RTCMODE[1:0] input pins of the crystal oscillator pad. For 32 kHz crystal operation, this
should be set to "01".
2
rst_cnt_omat
Reset Counter on Match: Writing logic 1 to this bit allows the counter to clear itself when a match
occurs. In this situation, the 40-bit counter clears on the next rising edge of the pre-scaled clock,
approximately 4 ms after the match occurs (the pre-scaled clock toggles at a rate of 256 Hz, given
a 32.768 kHz external crystal). Writing logic 0 to this bit allows the counter to increment
indefinitely while still allowing match events to occur.
1
rstb_cnt
Counter Reset: Writing logic 0 to this bit resets the 40-bit counter value to 0. Writing logic 1 allows
the counter to count.
0
xtal_en
Crystal Oscillator Enable: This bit controls the RTCXTLSEL output port that is connected to the
SELMODE input pin of the crystal oscillator. If a logic 0 is written to this bit, only the FPGA fabric
can be used to control the crystal oscillator EN and MODE[1:0] inputs. If a logic 1 is written to this
bit, only the RTC can be used to control the RTCXTLSEL and RTCMODE[1:0] inputs of the crystal
oscillator. This bit must be set to 1 to allow the RTC counter to function if the 1.5 V supply is off.
Notes:
1. Reset of all RTC states (except this Control/Status register) occurs asynchronously if VCC33UP = 0 or CTRL_STAT bit 7 (rtc_rst) is
written to 1.
2. Reset is removed synchronously after 2 rising edges of the ACM_CLK, following both VCC33UP = 1 and rtc_rst = 0.
3. Counter will first increment on the 64th rising edge of RTCCLK after all of the following are true: reset is removed, the rstb_cnt bit
is set to 1, and the cntr_en bit is set to 1; it will then increment every 128 RTCCLK cycles.
v2.0
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