COREAI-XX Datasheet, PDF (13/25 Pages) Actel Corporation – CoreAI

CoreAI
Table 14 • ADC Control Register 1 (low-order)
Bits
Name
Function
7
Reserved
Not used
6
ADCRESET
ADC Reset (write-only)
1 – The ADC is given an active high pulse (connected to the ADCRESET pin of the AB macro). Note
that this write-only bit is active for only one PCLK clock cycle (self-clearing).
0 – Normal (no operation or current conversion continues)
5
PWRDN
ADC Power Down
1 – The ADC is powered down.
0 – The ADC is powered up (normal operation).
4
VAREFSEL
ADC Voltage Reference Select
1 – Select external voltage reference (3.3 V max.) to be used (input on VAREF and GNDREF ports)
0 – Select internal voltage reference (2.56 V) to be used (output on VAREF port)
3:0
MODE[3:0]
ADC Mode Selection
The mode selection bits are used to select between 8-, 10-, and 12-bit ADC resolution.
(Refer to the Fusion datasheet for further information.)
Table 15 • ADC Control Register 1 (high-order)
Bits
Name
Function
7:0
TVC[7:0]
ADC Clock Divider
(Refer to the Fusion datasheet for further information.)
Table 16 • ADC Control Register 2 (low-order)
Bits
Name
Function
7:0
STC[7:0]
ADC Sample Time Control
(Refer to the Fusion datasheet for further information.)
Table 17 • ADC Control Register 2 (high-order)
Bits
Name
Function
7:6
Reserved
Not used
5
ADCSTART
ADC Start Conversion (write-only)
1 – The ADC starts an analog-to-digital conversion on the selected channel. Note that this write-
only bit is high for only one PCLK clock cycle (self-clearing).
0 – Normal (no operation or current conversion continues)
4:0
CHNUMBER[4:0] ADC Channel Number
This 5-bit value selects one of 32 analog channels that are fed to the analog MUX within the AB
macro.
(Refer to the Fusion datasheet for further information.)
Table 18 • ADC Control Register 3 (low-order)
Bits
Name
Function
7:0
CMSTB[7:0]
Current Monitor Strobes
These bits are connected to the CMSTB[7:0] pins of the AB macro.
(Refer to the Fusion datasheet for further information.)
v2.0
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