COREAI-XX Datasheet, PDF (1/25 Pages) Actel Corporation – CoreAI

CoreAI
Product Summary
Intended Use
• Analog Interface Control Using a Microprocessor/
Microcontroller and an Actel Fusion^TM Device
• Voltage, Current, and Temperature Monitoring
Using a Microprocessor/Microcontroller and an
Actel Fusion Device
Key Features
• ADC Conversions Controlled by MCU/MPU Writes
• AMBA APB Slave Interface (8- or 16-Bit Data
Widths Supported)
• 14 Maskable Interrupt Sources
• Internal Clock Divider for Generating Analog
Configuration MUX Clock
• Optional Read FIFO Stores up to 256 ADC
Conversion Results
• Analog Configuration MUX Can Be Configured by
SmartGen
Supported Families
• Fusion (including M7 devices)
Core Deliverables
• Evaluation Version
– Compiled RTL Simulation Model Fully
Supported in Actel Libero^® Integrated Design
Environment (IDE)
• Netlist Version
– Structural Verilog and VHDL Netlists (with and
without I/O Pads) Compatible with Actel
Designer Software Place-and-Route Tool
– Compiled RTL Simulation Model Fully
Supported in Actel Libero IDE
• RTL Version
– Verilog and VHDL Core Source Code
– Core Synthesis Scripts
• Testbench (Verilog and VHDL)
Synthesis and Simulation Support
• Directly Supported within Actel Libero IDE and
CoreConsole
• Synthesis: Synplicity^®, Synopsys^® (Design Compiler /
FPGA Compiler / FPGA Express), Exemplar
• Simulation: OVI-Compliant Verilog Simulators and
Vital-Compliant VHDL Simulators
Core Verification
• Comprehensive VHDL and Verilog Testbenches
• User Can Easily Modify User Testbench Using
Existing Format to Add Custom Tests
Contents
General Description ................................................... 1
Functional Block Descriptions ................................... 3
CoreAI Device Requirements ..................................... 3
CoreAI Verification ..................................................... 3
I/O Signal Descriptions ............................................... 4
Parameter/Generic Descriptions ................................ 6
Internal CoreAI Registers ......................................... 10
ACM Interface .......................................................... 18
RTC Operation .......................................................... 21
ADC Operation ......................................................... 22
Interrupt Logic ......................................................... 23
Ordering Information .............................................. 24
Datasheet Categories ............................................... 24
General Description
CoreAI (Analog Interface) allows for simple control of
the analog peripherals within the Fusion family of Actel
devices. Control may be implemented with an internal or
external microprocessor or microcontroller (such as
Core8051 or CoreMP7), or with user-created custom logic
within the FPGA fabric. The industry-standard AMBA
(Advanced Microcontroller Bus Architecture) APB
(Advanced Peripheral Bus) slave interface is used as the
primary control mechanism within CoreAI.
CoreAI instantiates the AB (Analog Block) macro, as
shown in Figure 1 on page 2. The AB macro includes the
March 2006
v2.0
1
© 2006 Actel Corporation