1553BBC-XX Datasheet, PDF (3/30 Pages) Actel Corporation – Core1553BBC MIL-STD-1553B Bus Controller

Core1553BBC MIL-STD-1553B Bus Controller
A single 1553B encoder takes each word to be
transmitted and serializes it using Manchester encoding.
The encoder includes independent logic to prevent the
BC from transmitting for greater than the allowed
period and to provide loopback fail logic. The loopback
logic monitors the received data and verifies that the
core has correctly received every word that is
transmitted. The encoder output is gated with the bus
enable signals to select which buses the RT should be
transmitting.
Since the BC knows which bus is in use at any time, only a
single decoder is required. The decoder takes the serial
Manchester received data from the bus and extracts the
received data words. The decoder requires a 12, 16, 20,
or 24 MHz clock to extract the data and the clock from
the serial stream.
The decoder contains a digital phased lock loop (PLL)
that generates a recovery clock used to sample the
incoming serial data. The data is then deserialized and
the 16-bit word decoded. The decoder detects whether a
command, status or data word has been received and
checks that no Manchester encoding or parity errors
occurred in the word.
The protocol controller block handles all the message
sequencing and error recovery. This is a complex state
machine that reads the 1553B message frames from the
memory and transmits them on the 1553B bus.
The CPU interface allows the system CPU to access the
control registers within the BC. It also allows the CPU to
directly access the memory connected to the backend
interface. These features can simplify system design.
The backend interface for the Core1553BBC allows a
simple connection to a memory device. The backend
interface can be configured to connect to either
synchronous or asynchronous memory devices. This
allows the core to be connected to synchronous logic or
memory within the FPGA or to external asynchronous
memory blocks. The interface supports a standard bus
request and grant protocol and provides a WAIT input,
allowing the core to interface to slow memory devices.
This allows the core to share system memory rather than
have its own dedicated memory block.
Core1553BBC Operation
A bus controller is responsible for sending data bus
commands, participating in data transfers, receiving
status responses, and monitoring the bus system. The
system CPU will create message lists in the BC memory, as
illustrated in Figure 3.
When started, the BC works its way through the message
lists. The Core1553B transmits the specified 1553B
command and data words, and receives the 1553B status
word and associated data words and writes them to the
BC memory. During this process, the BC monitors all
possible 1553B error conditions. If an RT does not
respond correctly, the BC will retry the message on both
the original bus and the alternate bus.
Instruction
List
INSTRUCTION
PARAMETER
INSTRUCTION
PARAMETER
INSTRUCTION
PARAMETER
Message
Block
MSGCMD
CW (RTRT RX)
CW (RTRT TX)
DATAPTR
SW (RTRT TX)
SW (RTRT RX)
TSW
Data
Block
32
Data Words
Figure 3 • Message Lists
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