1553BBC-XX Datasheet, PDF (18/30 Pages) Actel Corporation – Core1553BBC MIL-STD-1553B Bus Controller

Core1553BBC MIL-STD-1553B Bus Controller
Detailed Operation Flow
Table 17 shows the operations the core goes through in processing a message list containing two messages. The first
message is a BC-to-RT transfer of three words, and the second is an RT-to-BC transfer of three words.
Table 17 • Typical Operation
Time Memory Accesses
Operation
1553B Activity
Read first Instruction code
Read first Instruction parameter
Read first MSGCMD
Read first CW
Wait until the Inter-message gap expired
Read the DATAPTR
Transmit the command word
Read the 1st DW
Read the 2nd DW
Transmit the 1st data word
Read the 3rd DW
Transmit the 2nd data word
Transmit the 3rd data word
Wait for the RT Response Time
RT responds with SW
Write the SW to memory
Write the TSW to memory
Read second Instruction code
Read second instruction parameter
Read second MSGCMD
Read second CW
Wait until the Inter-message gap expired
Read the DATAPTR
Wait for the RT Response Time
Transmit the command word
RT responds with SW
Write the SW to memory
RT sends 1st data word
Write the 1st DW to memory
RT sends 2nd data word
Write the 2nd DW to memory
RT sends 3rd data word
Write the 2nd DW to memory
Write the TSW to memory
Read third Instruction code (HALT)
Generate the complete interrupt
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