1553BBC-XX Datasheet, PDF (1/30 Pages) Actel Corporation – Core1553BBC MIL-STD-1553B Bus Controller

Core1553BBC MIL-STD-1553B Bus Controller
Product Summary
Intended Use
• 1553B Bus Controller (BC)
• DMA Backend Interface to External Memory
Key Features
• Supports MIL-STD-1553B
• Interfaces to External RAM
– Supports up to 128kbytes of Memory
– Synchronous or Asynchronous Backend
Interface
– Backend Interface Identical to Core1553BRT
• Selectable Clock Rate of 12, 16, 20, or 24 MHz
• Provides Direct CPU Access to Memory
• Interfaces to Standard 1553B Transceivers
• Fully Automated Message Scheduling
– Frame Support
– Conditional Branching and Sub-routines
– Variable Inter-message Gaps and RT Response
Times
– Real Time Clock for Message Scheduling
– Asynchronous Message Support
Supported Families
• Fusion
• ProASIC3/E
• ProASIC^PLUS
• Axcelerator
• RTAX
• SX-A
• RTSX-S
Core Deliverables
• Netlist Version
– Compiled RTL Simulation Model, Compliant
with the Actel Libero™ Integrated Design
Environment (IDE)
– Compatible with the Actel Designer Place-and-
Route Tool
• RTL Version
– VHDL or Verilog Core Source Code
– Synthesis Scripts
• Actel-Developed Testbenches, VHDL and Verilog
Synthesis and Simulation Support
• Synthesis: Synplicity^®, Synopsys^® (Design Compiler^®/
FPGA Compiler^TM/FPGA Express^TM), Exemplar^TM
• Simulation: Vital-Compliant VHDL Simulators and
OVI-Compliant Verilog Simulators
Verification and Compliance
• Actel-Developed Simulation Testbench
• Core Implemented on the 1553B BC Development
System
• Third-Party 1553B Compliance Testing of the
1553B Encoder and Decoder Blocks Implemented
in an A54SXA32-STD Device
Development System (Optional)
• Complete 1553B BC Implementation in an SX-A
Device
• Includes a PCI Interface for Host CPU Connection
• Includes Transceivers and Bus Termination
Components
Contents
General Description ................................................... 2
Core1553BBC Device Requirements .......................... 4
Core1553BBC Verification and Compliance .............. 4
MIL-STD-1553B Bus Overview .................................... 4
I/O Signal Descriptions ............................................. 6
Bus Transceivers ........................................................ 20
Development System ............................................... 20
Typical BC System ..................................................... 22
Specifications ............................................................ 24
Ordering Information .............................................. 28
List of Changes ......................................................... 29
Datasheet Categories ............................................... 29
December 2005
v4.0
1
© 2005 Actel Corporation