RT3PE3000L-1FG484B Datasheet, PDF (100/144 Pages) Actel Corporation – Radiation-Tolerant ProASIC3 Low-Power Space- Flight Flash FPGAs

Radiation-Tolerant ProASIC3 FPGAs
Table 2-133 • RT ProASIC3 CCC/PLL Specification
For Devices Operating at 1.5 V DC Core Voltage
Parameter
Min.
Typ.
Max. Units
Clock Conditioning Circuitry Input Frequency f_{IN_CCC}
Clock Conditioning Circuitry Output Frequency
f_{OUT_CCC}
Serial Clock (SCLK) for Dynamic PLL⁵
Delay Increments in Programmable Delay Blocks^{1, 2}
1.5
350 MHz
0.75
350 MHz
110 MHz
200
ps
Number of Programmable Values in Each
32
Programmable Delay Block
Input Period Jitter
1.5
ns
CCC Output Peak-to-Peak Period Jitter F_{CCC_OUT}
Max Peak-to-Peak Period Jitter
1 Global
Network
Used
3 Global
Networks
Used
0.75 MHz to 24 MHz
0.50%
0.70%
24 MHz to 100 MHz
1.00%
1.20%
100 MHz to 250 MHz
1.75%
2.00%
250 MHz to 350 MHz
2.50%
5.60%
Acquisition Time
LockControl = 0
300
µs
LockControl = 1
6.0
ms
Tracking Jitter
LockControl = 0
1.6
ns
LockControl = 1
0.8
ns
Output Duty Cycle
Delay Range in Block: Programmable Delay 1 ^{1, 2}
Delay Range in Block: Programmable Delay 2 ^{1, 2}
Delay Range in Block: Fixed Delay ^{1, 2}
48.5
0.6
0.025
2.2
51.5
%
5.56
ns
5.56
ns
ns
Notes:
1. This delay is a function of voltage and temperature. See Table 2-5 on page 2-8 for deratings.
2. T_J = 25°C, V_CC = 1.5 V
3. Maximum value obtained for a Std. speed grade device in worst-case military conditions. For specific
junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.
4. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input
clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by period
jitter parameter.
5. Maximum value obtained for a -1 speed grade device in worst-case military conditions. For specific junction
temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.
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